公开(公告)号：GB2507754A

公开(公告)日：2014-05-14

申请号：GB201220087

申请日：2012-11-07

Applicant: IBM

Inventor： WERNER TOBIAS ,  PAYER STEFAN ,  POLIG RAPHAEL ,  KUGEL MICHAEL

IPC: G06F17/50

Abstract: The application relates to scalable circuit schematic. A computer-readable memory comprises first data representative of a topology of a circuit comprising a first circuit clement and a second circuit element, and second data representative of a scaling rule for the first circuit clement as a function of the second circuit element. A data processing method comprising retrieving first data representative of a topology of a circuit comprising a first circuit clement and a second circuit clement from a memory, retrieving second data representative of a scaling rule for the first circuit element as a function or the second circuit element from the memory, receiving a user input representative of a scaling factor, generating third data representative of an instance of the second circuit element using the scaling factor, and generating data representative of an instance of the first circuit element using the scaling factor, the scaling rule and the third data. The scaling rule may be for a capacitance as a function of load, resistance as a function of a transistor, a transistor as a function of resistance or a transistor as a function of another transistor.

公开(公告)号：DE112019004223T5

公开(公告)日：2021-05-20

申请号：DE112019004223

申请日：2019-10-22

Applicant: IBM

Inventor： PILLE JUERGEN ,  FRISCH ALBERT ,  WERNER TOBIAS ,  SAUTTER ROLF ,  WENDEL DIETER

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/8239 ,  H01L27/06 ,  H01L27/11

Abstract: Eine Ausführungsform kann eine mikroelektronische Einheit enthalten. Die mikroelektronische Einheit kann ein erstes Paar Transistoren enthalten, die vertikal gestapelt und in Reihe geschaltet sind. Beide Transistoren des ersten Paars Transistoren sind vom selben Typ. Die mikroelektronische Einheit kann ein zweites Paar Transistoren enthalten, die parallel geschaltet sind. Das zweite Paar Transistoren ist von einem anderen Typ als das erste Paar Transistoren. Das erste Paar Transistoren und das zweite Paar Transistoren sind im Wesentlichen senkrecht zu der Mehrzahl Schichten angeordnet.

公开(公告)号：GB2512641A

公开(公告)日：2014-10-08

申请号：GB201306122

申请日：2013-04-05

Applicant: IBM

Inventor： POLIG RAPHAEL ,  WERNER TOBIAS ,  PENTH SILKE ,  KUGEL MICHAEL

IPC: G11C8/10 ,  G11C8/08 ,  G11C8/12

Abstract: An SRAM array 100 comprising multiple cell cores 102, 104, 106, 108 to store and retrieve data, each cell core comprising a plurality of SRAM cells 112, and wherein at least two corresponding cell cores 102, 104 and 106, 108 build a cell core row 122. A word decoder 110 configured to decode incoming address signals 116 representing a storage address into a single word line 114, so that one storage word is activated. The word decoder 110 comprises, a cell core select unit (306, figure 3) configured to generate a cell core row select signal (402, figure 4) from a combination of a first part (412) of the incoming address signals 116 and a received clock signal (308, figure 4), a decoding element (302, 304, figure 4) for each cell core row 122, the decoding element comprising a first decoding block (404, figure 4) for decoding a second part (414, figure 4) of the incoming address signals 116 for building an upper portion (408) of word line select signals (422) and a second decoding block (406 figure 4) for decoding a third part (416) of the incoming address signals 116 for building a lower portion (410, figure 4) of word line select signals (422), a word line driver (418, 420) for each cell core row (122) configured to combine the upper portion (408) of the word line select signal (422) from the first decoding block (404) and the lower portion (410) of the word line select signal (422) from the second decoding block (406) to form a unique word line signal 114 per storage address.