公开(公告)号：JP2000322258A

公开(公告)日：2000-11-24

申请号：JP2000116777

申请日：2000-04-18

Applicant: IBM

Inventor： FEISTE KURT ALAN ,  JOHN STEFAN MUHICHI ,  WHITE STEVEN WAYNE

IPC: G06F9/38

Abstract: PROBLEM TO BE SOLVED: To obtain a method which prevents an error caused by collision between preload and a storage instruction. SOLUTION: A processor 100 includes a preload queue 160 for storage of plural preload entries. Each preload entry is related to a preload instruction and includes defined address and byte count and a related identifier. A comparison unit 170 related to the preload queue 160 discriminates each of preload entries related to preload instructions which collide with older storage instructions. The oldest preload instruction related to one of these preload entries indicates target preload. In order to correct the collision between the target preload and the storage instruction, this target preload and all instructions executed after the target preload are flashed.

公开(公告)号：JPH10320198A

公开(公告)日：1998-12-04

申请号：JP9133098

申请日：1998-04-03

Applicant: IBM

Inventor： FEISTE KURT ALAN ,  MUHICH JOHN STEPHEN ,  THATCHER LARRY EDWARD ,  WHITE STEVEN WAYNE

IPC: G06F9/38 ,  G06F12/00

Abstract: PROBLEM TO BE SOLVED: To transfer stored data to a necessary load instruction without stalling the long instruction until storage completion by transferring store data to the load instruction when a store instruction is already converted, a load address range is included in a store address range, and the store data are usable. SOLUTION: This is a method for transferring data as the result of a store instruction which does not have updated data to the load instruction and a CPU 120 judges whether or not there is a common byte between the address of the load instruction and the address of the store instruction. Further, it is judged whether or not the load instruction is logically behind the store instruction. When there is the common byte between the address of the load instruction and the address of the store instruction and when the load instruction is logically behind the store instruction, the data is transferred to the load instruction.

公开(公告)号：MY121300A

公开(公告)日：2006-01-28

申请号：MYPI9800941

申请日：1998-03-04

Applicant: IBM

Inventor： FEISTE KURT ALAN ,  MUNICH JOHN STEPHEN ,  THATCHER LARRY EDWARD ,  WHITE STEVEN WAYNE

IPC: G06F9/34 ,  G06F9/38 ,  G06F12/00

Abstract: IN A SUPERSCALAR PROCESSOR (210) IMPLEMENTING OUT-OF-ORDER DISPATCHING AND EXECUTION OF LOAD AND STORE INSTRUCTIONS, WHEN A STORE INSTRUCTION HAS ALREADY BEEN TRANSLATED, THE LOAD ADDRESS RANGE OF A LOAD INSTRUCTION IS CONTAINED WITHIN THE ADDRESS RANGE OF THE STORE INSTRUCTION, AND THE DATA ASSOCIATED WITH THE STORE INSTRUCTION IS AVAILABLE, THEN THE DATA ASSOCIATED WITH THE STORE INSTRUCTION IS FORWARDED TO THE LOAD INSTRUCTION SO THAT THE LOAD INSTRUCTION MAY CONTINUE EXECUTION WITHOUT HAVING TO BE STALLED OR FLUSHED.

公开(公告)号：AT242509T

公开(公告)日：2003-06-15

申请号：AT98301659

申请日：1998-03-06

Applicant: IBM

Inventor： FEISTE KURT ALAN ,  MUHICH JOHN STEPHEN ,  THATCHER LARRY EDWARD ,  WHITE STEVEN WAYNE

IPC: G06F9/38 ,  G06F12/00

Abstract: In a superscalar processor implementing out-of-order dispatching and execution of load and store instructions, when a store instruction has already been translated, the load address range of a load instruction is contained within the address range of the store instruction, and the data associated with the store instruction is available, then the data associated with the store instruction is forwarded to the load instruction so that the load instruction may continue execution without having to be stalled or flushed.

公开(公告)号：DE69815201D1

公开(公告)日：2003-07-10

申请号：DE69815201

申请日：1998-03-06

Applicant: IBM

Inventor： FEISTE KURT ALAN ,  MUHICH JOHN STEPHEN ,  THATCHER LARRY EDWARD ,  WHITE STEVEN WAYNE

IPC: G06F9/38 ,  G06F12/00

Abstract: In a superscalar processor implementing out-of-order dispatching and execution of load and store instructions, when a store instruction has already been translated, the load address range of a load instruction is contained within the address range of the store instruction, and the data associated with the store instruction is available, then the data associated with the store instruction is forwarded to the load instruction so that the load instruction may continue execution without having to be stalled or flushed.

公开(公告)号：GB2322718A

公开(公告)日：1998-09-02

申请号：GB9725995

申请日：1997-12-09

Applicant: IBM

Inventor： HICKS TROY NEAL ,  LE HUNG OUI ,  MUHICH JOHN STEPHEN ,  WHITE STEVEN WAYNE

IPC: G06F9/38

Abstract: A pre-execution queue PEQ 42 stores instructions for an information handling system, and schedules the issuing of these instructions to at least one execution cluster 54, 56, each comprising an early, 46, 50, and a late, 48, 52, execution unit. Each execution unit executes an instruction dispatched from PEQ 42, and generates and forwards a result to another unit for execution of a further instruction. This result data forwarding takes longer if it is between units of different clusters. In particular, a result from early unit 46 is available to late unit 48 in the same cluster 54 in the same clock cycle. The instruction scheduling takes into account this non-uniform forwarding of result data (for example, by "pairing" dependent instructions and issuing them to the same cluster), and ensures that only instructions whose operands are available are scheduled. PEQ 42 classifies and groups the instructions into buckets with associated selection priorities (fig. 6). Instructions can be dynamically reassigned to buckets in response to execution delays and priority conflicts.

公开(公告)号：DE68923437T2

公开(公告)日：1996-03-07

申请号：DE68923437

申请日：1989-11-23

Applicant: IBM

Inventor： WHITE STEVEN WAYNE

IPC: G06F12/10

Abstract: In a data processing system including bulk storage and paging storage, a two 64-pair DLAT structure is used, one for 4KB pages and one for 1MB pages. Each DLAT is two-way set associative with pairs of entries, each entry representing a page. The DLATs are interrogated in parallel by a hash combination of appropriate intermediate virtual address bit and each entry includes a high order page identifier, a real address and a valid bit, access being provided to the real address if the identifier and the valid bit are both satisfied. There is no page overlap.

公开(公告)号：DE68923437D1

公开(公告)日：1995-08-17

申请号：DE68923437

申请日：1989-11-23

Applicant: IBM

Inventor： WHITE STEVEN WAYNE

IPC: G06F12/10

Abstract: In a data processing system including bulk storage and paging storage, a two 64-pair DLAT structure is used, one for 4KB pages and one for 1MB pages. Each DLAT is two-way set associative with pairs of entries, each entry representing a page. The DLATs are interrogated in parallel by a hash combination of appropriate intermediate virtual address bit and each entry includes a high order page identifier, a real address and a valid bit, access being provided to the real address if the identifier and the valid bit are both satisfied. There is no page overlap.