公开(公告)号：DE3173744D1

公开(公告)日：1986-03-20

申请号：DE3173744

申请日：1981-10-30

Applicant: IBM DEUTSCHLAND ,  IBM

Inventor： HEUBER KLAUS ,  WIEDMANN SIEGFRIED DR

IPC: G11C11/414 ,  G11C11/416 ,  G11C11/40

Abstract: A method of and a circuit arrangement for reading an integrated MTL(I2L) store are described, wherein prior to or during a read operation, line capacities are discharged and in addition to the word line drivers and the bit line drivers, a read/write circuit is provided. Simultaneously with the selection of a word line (WL) or with a slight time delay (t1), two identical current sources (IRD0) are connected by means of two switches (S0 and S1) to the relevant bit lines (B0 and B1). As a result, the two injectors of the two bit line PNP transistors (T1 and T4) are supplied with the same currents. In a second phase (t2), the current sources (IRD0) are switched off so that the duration of the second time phase (t2) considerably exceeds the storage time constant ( tau e) of the bit line PNP transistor (T4) connected to the switched "OFF" NPN transistor (T3) of a cell. The effective storage time constant ( tau SAT) of the bit line PNP transistor (T1 ), connected to the switched on NPN cell transistor (T2), considerably exceeds the storage time constant ( tau e). As a result of the different time constants ( tau e and tau SAT), the two storage charges (Q1 and Q4) are discharged at different rates during the third phase (t3), thus generating a very fast and high output signal ( DELTA VBL=VS).

公开(公告)号：DE3070394D1

公开(公告)日：1985-05-02

申请号：DE3070394

申请日：1980-11-26

Applicant: IBM DEUTSCHLAND ,  IBM

Inventor： BERGER HORST DR ,  WIEDMANN SIEGFRIED DR

IPC: G11C11/411 ,  G11C8/16 ,  G06F13/00 ,  G11C8/00 ,  G11C11/40 ,  H03K3/286

Abstract: A multiaddressable highly integrated semiconductor storage is provided, the storage locations of which are addressable by several independent address systems for parallel reading and/or writing. The storage locations are each made up of n storage elements. One storage location consists, for example, of at least two flip-flops which, via coupling elements are connected to associated separate bit and word lines. Each storage location has at least three independently selectable or addressable entry/exit ports permitting the following operations to be executed in parallel: Read word A, read word B, write word C as well as any combination of two or individual ones of those operations. The number of read ports can be increased by providing further address systems and by substituting triple, quadruple, etc., storage cells for a cell pair.

公开(公告)号：DE3174546D1

公开(公告)日：1986-06-12

申请号：DE3174546

申请日：1981-05-30

Applicant: IBM DEUTSCHLAND ,  IBM

Inventor： WIEDMANN SIEGFRIED DR

IPC: G11C11/411 ,  H01L21/8226 ,  H01L21/8228 ,  H01L21/8229 ,  H01L27/082 ,  H01L27/102 ,  H01L27/02 ,  G11C11/40

Abstract: A memory is described comprising static MTL memory cells for high operation speeds. The cell or primary injectors and the bit line injectors are coupled to each other by an angular injection coupling via the low-resistivity base region of the cell flip-flop transistors. This results in a signal path with reduced series resistance and thus higher signals and a faster read operation obtainable. The density is additionally increased by using in common the primary injectors and the bit line injectors of adjacent cells of the array.

公开(公告)号：DE3063452D1

公开(公告)日：1983-07-07

申请号：DE3063452

申请日：1980-06-03

Applicant: IBM

Inventor： HEUBER KLAUS ,  WIEDMANN SIEGFRIED DR

IPC: G11C11/414 ,  G11C7/00 ,  G11C11/24 ,  G11C11/40 ,  G11C11/402 ,  G11C11/4063 ,  G11C11/411 ,  G11C11/416

Abstract: A method and arrangement is provided for selecting and discharging a pair of bit lines of a plurality of charged pairs of bit lines of a memory circuit having cells of the merged transistor logic type. A selected pair of bit lines is discharged through a selected cell coupled to the selected pair of bit lines while simultaneously the remaining or non-selected pairs of bit lines are discharged through a common switch into non-selected word lines.

公开(公告)号：DE3068118D1

公开(公告)日：1984-07-12

申请号：DE3068118

申请日：1980-09-15

Applicant: IBM

Inventor： HEUBER KLAUS ,  KLINK ERICH ,  RUDOLPH VOLKER DR ,  WIEDMANN SIEGFRIED DR

IPC: G11C11/414 ,  G11C11/40 ,  G11C11/4063 ,  G11C11/413 ,  H01L21/822 ,  H01L21/8229 ,  H01L27/02 ,  H01L27/04 ,  H01L27/102

Abstract: Disclosed is a simulated storage cell structure for use as a reference voltage generator in a semiconductor store fabricated in Merged Transistor Logic (MTL) technology. The simulated storage cell structure includes n elongated regions of P-type diffusion arranged in parallel to each other in an N-type trough of semiconductor material. The elongated P-type regions are alternately designed as collector and Injector strips.

公开(公告)号：CH596670A5

公开(公告)日：1978-03-15

申请号：CH254776

申请日：1976-03-02

Applicant: IBM

Inventor： BERGER HORST DR ,  WIEDMANN SIEGFRIED DR

IPC: H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/082 ,  H01L29/73 ,  H03K19/091 ,  H03K19/08

Abstract: The disclosure is directed to the circuitry and monolithic semiconductor structure of Current Hogging Injection Logic Configurations. More specifically the disclosure relates to a semiconductor arrangement for the basic components of a highly integratable, logic semiconductor circuit concept predicated on multicollector inverter transistors which are fed by means of a carrier injection into their emitter/base zones.

公开(公告)号：DE3068176D1

公开(公告)日：1984-07-19

申请号：DE3068176

申请日：1980-06-18

Applicant: IBM

Inventor： HEUBER KLAUS ,  WIEDMANN SIEGFRIED DR

IPC: G11C11/41 ,  G05F3/20 ,  G05F3/22 ,  G11C7/00 ,  G11C11/40 ,  G11C11/402 ,  G11C11/411 ,  G11C11/414 ,  G11C11/416 ,  H01L21/8229 ,  H01L27/102

Abstract: Disclosed is a restore circuit for restoring an integrated semiconductor storage array having storage cells consisting of bipolar transistors. The restore circuit includes a reference voltage generator, an impedance converter, and switches to connect the reference voltage generator and the impedance converter to the storage array. The reference voltage generating circuit includes a current source and at least one reference storage cell identical in construction to the storage cells of the array. The reference voltage generating circuit provides a reference voltage to the impedance converter which supplies a second reference voltage to the array at a greatly reduced impedance. The equivalent circuit of the storage cells is that of a capacitor in parallel with a diode. Thus, the impedance converter provides an initial surge of capacitive current which restores the cells, followed by a standby current which is a function of the diode characteristics of the cell equivalent circuit.

公开(公告)号：DE3063344D1

公开(公告)日：1983-07-07

申请号：DE3063344

申请日：1980-09-15

Applicant: IBM

Inventor： WIEDMANN SIEGFRIED DR ,  BERGER HORST DR

IPC: G11C5/06 ,  G11C8/00 ,  G11C11/40 ,  G11C11/411 ,  H01L27/02 ,  H01L27/06 ,  H01L27/07 ,  H01L27/102

公开(公告)号：DE2964971D1

公开(公告)日：1983-04-07

申请号：DE2964971

申请日：1979-10-31

Applicant: IBM

Inventor： HEUBER KLAUS ,  WIEDMANN SIEGFRIED DR

IPC: G11C11/41 ,  G11C11/24 ,  G11C11/40 ,  G11C11/402 ,  G11C11/411 ,  G11C11/414 ,  G11C11/416 ,  H01L27/02