公开(公告)号：DE3173744D1

公开(公告)日：1986-03-20

申请号：DE3173744

申请日：1981-10-30

Applicant: IBM DEUTSCHLAND ,  IBM

Inventor： HEUBER KLAUS ,  WIEDMANN SIEGFRIED DR

IPC: G11C11/414 ,  G11C11/416 ,  G11C11/40

Abstract: A method of and a circuit arrangement for reading an integrated MTL(I2L) store are described, wherein prior to or during a read operation, line capacities are discharged and in addition to the word line drivers and the bit line drivers, a read/write circuit is provided. Simultaneously with the selection of a word line (WL) or with a slight time delay (t1), two identical current sources (IRD0) are connected by means of two switches (S0 and S1) to the relevant bit lines (B0 and B1). As a result, the two injectors of the two bit line PNP transistors (T1 and T4) are supplied with the same currents. In a second phase (t2), the current sources (IRD0) are switched off so that the duration of the second time phase (t2) considerably exceeds the storage time constant ( tau e) of the bit line PNP transistor (T4) connected to the switched "OFF" NPN transistor (T3) of a cell. The effective storage time constant ( tau SAT) of the bit line PNP transistor (T1 ), connected to the switched on NPN cell transistor (T2), considerably exceeds the storage time constant ( tau e). As a result of the different time constants ( tau e and tau SAT), the two storage charges (Q1 and Q4) are discharged at different rates during the third phase (t3), thus generating a very fast and high output signal ( DELTA VBL=VS).

公开(公告)号：DE3063452D1

公开(公告)日：1983-07-07

申请号：DE3063452

申请日：1980-06-03

Applicant: IBM

Inventor： HEUBER KLAUS ,  WIEDMANN SIEGFRIED DR

IPC: G11C11/414 ,  G11C7/00 ,  G11C11/24 ,  G11C11/40 ,  G11C11/402 ,  G11C11/4063 ,  G11C11/411 ,  G11C11/416

Abstract: A method and arrangement is provided for selecting and discharging a pair of bit lines of a plurality of charged pairs of bit lines of a memory circuit having cells of the merged transistor logic type. A selected pair of bit lines is discharged through a selected cell coupled to the selected pair of bit lines while simultaneously the remaining or non-selected pairs of bit lines are discharged through a common switch into non-selected word lines.

公开(公告)号：FR2295524A1

公开(公告)日：1976-07-16

申请号：FR7534718

申请日：1975-11-05

Applicant: IBM

Inventor： HEUBER KLAUS ,  KLEIN WILFRIED ,  NAJMANN KNUT ,  REMSHARDT ROLF

IPC: G11C11/41 ,  G11C11/34 ,  G11C11/416 ,  H03K3/287 ,  H03K5/02 ,  G11C7/00 ,  G11C11/40

Abstract: This teaches a sense circuit for an integrated memory storage system in which the storage cell output is detected by a differential amplifier, controlling a flip-flop, serving as a latch, having load elements which also function as the load elements of the latch to ensure an optimum power and speed product. The latch can be coupled to an output driver circuit through a current switch which shares common elements with the latch to assure that the latch remains symmetrical even when used with an output driver having asymmetrical control.

公开(公告)号：FR2374725A1

公开(公告)日：1978-07-13

申请号：FR7733079

申请日：1977-10-24

Applicant: IBM

Inventor： HEUBER KLAUS ,  KLEIN WILFRIED ,  NAJMANN KNUT ,  WERNICKE FRIEDRICH ,  WIEDMANN SIEGFRIED K

IPC: G11C11/41 ,  G11C7/04 ,  G11C11/411 ,  G11C11/414 ,  G11C11/416 ,  G11C11/34 ,  G11C7/00

公开(公告)号：FR2304991A1

公开(公告)日：1976-10-15

申请号：FR7602996

申请日：1976-01-29

Applicant: IBM

Inventor： BERGER HORST ,  HEUBER KLAUS ,  KLEIN WILFRIED ,  NAJMANN KNUT

IPC: G11C11/414 ,  G11C11/411 ,  G11C11/416 ,  G11C11/40

Abstract: The invention relates to a circuit arrangement for operating the read/write cycles of an integrated semiconductor memory storage system whose storage cells consist of flip flops with bipolar switching transistors, Schottky diodes as read/write elements coupling the cell to the bit lines, and high-resistivity resistors, or transistors controlled as current sources, as load elements, in several phases.

公开(公告)号：FR2293766A1

公开(公告)日：1976-07-02

申请号：FR7532210

申请日：1975-10-13

Applicant: IBM

Inventor： HEUBER KLAUS ,  KLEIN WILFRIED ,  NAJMANN KNUT ,  WIEDMANN SIEGFRIED

IPC: G11C11/414 ,  G11C11/411 ,  G11C11/415 ,  G11C7/00 ,  G11C11/40

公开(公告)号：DE3068176D1

公开(公告)日：1984-07-19

申请号：DE3068176

申请日：1980-06-18

Applicant: IBM

Inventor： HEUBER KLAUS ,  WIEDMANN SIEGFRIED DR

IPC: G11C11/41 ,  G05F3/20 ,  G05F3/22 ,  G11C7/00 ,  G11C11/40 ,  G11C11/402 ,  G11C11/411 ,  G11C11/414 ,  G11C11/416 ,  H01L21/8229 ,  H01L27/102

Abstract: Disclosed is a restore circuit for restoring an integrated semiconductor storage array having storage cells consisting of bipolar transistors. The restore circuit includes a reference voltage generator, an impedance converter, and switches to connect the reference voltage generator and the impedance converter to the storage array. The reference voltage generating circuit includes a current source and at least one reference storage cell identical in construction to the storage cells of the array. The reference voltage generating circuit provides a reference voltage to the impedance converter which supplies a second reference voltage to the array at a greatly reduced impedance. The equivalent circuit of the storage cells is that of a capacitor in parallel with a diode. Thus, the impedance converter provides an initial surge of capacitive current which restores the cells, followed by a standby current which is a function of the diode characteristics of the cell equivalent circuit.

公开(公告)号：DE2964971D1

公开(公告)日：1983-04-07

申请号：DE2964971

申请日：1979-10-31

Applicant: IBM

Inventor： HEUBER KLAUS ,  WIEDMANN SIEGFRIED DR

IPC: G11C11/41 ,  G11C11/24 ,  G11C11/40 ,  G11C11/402 ,  G11C11/411 ,  G11C11/414 ,  G11C11/416 ,  H01L27/02

公开(公告)号：IT8023021D0

公开(公告)日：1980-06-26

申请号：IT2302180

申请日：1980-06-26

Applicant: IBM

Inventor： HEUBER KLAUS ,  WIEDMANN SIEGFRIED KURT

IPC: G11C11/41 ,  G05F3/20 ,  G05F3/22 ,  G11C7/00 ,  G11C11/40 ,  G11C11/402 ,  G11C11/411 ,  G11C11/414 ,  G11C11/416 ,  H01L21/8229 ,  H01L27/102 ,  G11C

Abstract: Disclosed is a restore circuit for restoring an integrated semiconductor storage array having storage cells consisting of bipolar transistors. The restore circuit includes a reference voltage generator, an impedance converter, and switches to connect the reference voltage generator and the impedance converter to the storage array. The reference voltage generating circuit includes a current source and at least one reference storage cell identical in construction to the storage cells of the array. The reference voltage generating circuit provides a reference voltage to the impedance converter which supplies a second reference voltage to the array at a greatly reduced impedance. The equivalent circuit of the storage cells is that of a capacitor in parallel with a diode. Thus, the impedance converter provides an initial surge of capacitive current which restores the cells, followed by a standby current which is a function of the diode characteristics of the cell equivalent circuit.

公开(公告)号：IT1151018B

公开(公告)日：1986-12-17

申请号：IT2302180

申请日：1980-06-26

Applicant: IBM

Inventor： HEUBER KLAUS ,  WIEDMANN SIEGFRIED KURT

IPC: G11C11/41 ,  G05F3/20 ,  G05F3/22 ,  G11C7/00 ,  G11C11/40 ,  G11C11/402 ,  G11C11/411 ,  G11C11/414 ,  G11C11/416 ,  H01L21/8229 ,  H01L27/102 ,  G11C

Abstract: Disclosed is a restore circuit for restoring an integrated semiconductor storage array having storage cells consisting of bipolar transistors. The restore circuit includes a reference voltage generator, an impedance converter, and switches to connect the reference voltage generator and the impedance converter to the storage array. The reference voltage generating circuit includes a current source and at least one reference storage cell identical in construction to the storage cells of the array. The reference voltage generating circuit provides a reference voltage to the impedance converter which supplies a second reference voltage to the array at a greatly reduced impedance. The equivalent circuit of the storage cells is that of a capacitor in parallel with a diode. Thus, the impedance converter provides an initial surge of capacitive current which restores the cells, followed by a standby current which is a function of the diode characteristics of the cell equivalent circuit.