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    ADJUSTING SUBPIXEL INTENSITY VALUES BASED UPON LUMINANCE CHARACTERISTICS OF THE SUBPIXELS IN LIQUID CRYSTAL DISPLAYS
    1.
    发明申请
    ADJUSTING SUBPIXEL INTENSITY VALUES BASED UPON LUMINANCE CHARACTERISTICS OF THE SUBPIXELS IN LIQUID CRYSTAL DISPLAYS 审中-公开
    基于液晶显示器中SUBPIXEL的发光特性调整SUBPIXEL强度值

    公开(公告)号：WO02059685A2

    公开(公告)日：2002-08-01

    申请号：PCT/US0149538

    申请日：2001-12-20

    Applicant: IBM

    Inventor： GREIER PAUL F ,  HO KENNETH C ,  KAUFMAN RICHARD I ,  MILLMAN STEVEN E ,  THOMPSON GERHARD R ,  WRIGHT STEVEN L ,  WU CHAI W

    IPC: G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00 ,  G02F

    CPC classification number: G09G3/3611 ,  G09G3/2051 ,  G09G3/3614 ,  G09G5/006 ,  G09G2300/0443 ,  G09G2300/0447 ,  G09G2320/0276 ,  G09G2320/028

    Abstract: Viewing angle characteristics of a liquid crystal display (LCD) (112) are improved by reducing the number of subpixels in an image with mid-tone luminance values. In a preferred embodiment, a first table of entries associating subpixel intensity values and subpixel luminance values for a LCD in at least one viewing angle direction is provided. A target intensity value is determined from the first table, corresponding to the average subpixel luminance over a small number of adjacent subpixels. A second table of entries associates the target intensity values with intensity values above and below the target. The adjacent subpixel intensity values are modified according to the second table, thereby reducing the number of subpixels with mid-tone luminance values. The subpixel data is preferably processed within a portion of an application-specific integrated circuit (ASIC) (303), contained within the display module (112-2).

    Abstract translation: 通过用中间色调亮度值减少图像中的子像素的数量来改善液晶显示器（LCD）（112）的视角特性。 在优选实施例中，提供了将至少一个视角方向上的LCD的子像素强度值和子像素亮度值相关联的条目的第一表。 从第一表确定对应于少数相邻子像素上的平均子像素亮度的目标强度值。 第二个条目表将目标强度值与目标上方和下方的强度值相关联。 根据第二表修改相邻的子像素强度值，从而减少具有中间色调亮度值的子像素的数量。 子像素数据优选地在包含在显示模块（112-2）内的专用集成电路（ASIC）（303）的一部分内进行处理。

    UNPINNED OXIDE-COMPOUND SEMICONDUCTOR STRUCTURES AND METHOD OF FORMING SAME
    3.
    发明专利
    UNPINNED OXIDE-COMPOUND SEMICONDUCTOR STRUCTURES AND METHOD OF FORMING SAME 未知

    公开(公告)号：CA1308818C

    公开(公告)日：1992-10-13

    申请号：CA597294

    申请日：1989-04-20

    Applicant: IBM

    Inventor： BATEY JOHN ,  TIWARI SANDIP ,  WRIGHT STEVEN L

    IPC: H01L29/78 ,  H01L21/203 ,  H01L21/205 ,  H01L21/28 ,  H01L21/31 ,  H01L21/314 ,  H01L21/336 ,  H01L29/267 ,  H01L29/43 ,  H01L29/60

    Abstract: UNPINNED OXIDE-COMPOUND SEMICONDUCTOR STRUCTURES AND METHOD OF FORMING SAME Unpinned epitaxial metal-oxide-compound semiconductor structures are disclosed and a method of fabricating such structures is described. Epitaxial layers of compound semiconductor are grown by MBE which result in the formation of a smooth surface having a stabilized reconstruction. An elemental semiconductor layer is deposited epitaxially in situ with the compound semiconductor layer which unpins the surface Fermi level. A layer of insulator material is then deposited on the elemental semiconductor layer by PECVD. In one embodiment, the compound semiconductor is GaAs and the elemental semiconductor is Si. The insulator material is a layer of high quality SiO2. A metal gate is deposited on the SiO2 layer to form an MOS device. The epitaxial GaAs layer has a density of states which permits the interface Fermi level to be moved through the entire forbidden energy gap. In another embodiment, the SiO2 deposition completely consumes the interface Si layer so that the resulting MOS device comprises SiO2 directly overlying the GaAs layer. Y0988-028

    MODE SELECTION LAYER FOR SEMICONDUCTOR DEVICE
    4.
    发明专利
    MODE SELECTION LAYER FOR SEMICONDUCTOR DEVICE 未知

    公开(公告)号：CA1223673A

    公开(公告)日：1987-06-30

    申请号：CA504661

    申请日：1986-03-20

    Applicant: IBM

    Inventor： SOLOMON PAUL M ,  WRIGHT STEVEN L

    IPC: H01L29/812 ,  H01L21/338 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H01L27/095 ,  H01L29/10 ,  H01L29/778 ,  H01L29/76

    Abstract: Mode Selection Layer for Semiconductor Device A field effect transistor structure suitable for use in an array of such structures disposed on a common substrate is formed with a source terminal, a drain terminal, and a gate terminal upon an upper surface of a semiconductor chip. The chip includes a first layer and a second layer, the first layer being grown epitaxially upon the second layer. The first layer forms a part of the gate terminal and the second layer includes a charge conduction channel coupling the source terminal and the drain terminal. A pocket layer is disposed in the second layer beneath the terminals of the transistor structure and is doped with either an donor dopant or an acceptor dopant for altering the electric field at the conduction channel to insert electrons or remove electrons therefrom so as to convert an operating mode from either an enhancement mode to a depletion mode or from a depletion mode to an enchancement made. A substrate with a terminal on the backside thereof may be placed contiguous the bottom of said second layer, the back terminal being applied to a negative source of voltage for a transistor structure of n-channel format. The semiconductor material of the chip is a obtained from compounds of elements of the groups III and V of the periodic table.

    GERMANIUM CHANNEL SILICON MOSFET
    7.
    发明专利
    GERMANIUM CHANNEL SILICON MOSFET 未知

    公开(公告)号：CA1298670C

    公开(公告)日：1992-04-07

    申请号：CA611437

    申请日：1989-09-14

    Applicant: IBM

    Inventor： SOLOMON PAUL M ,  WRIGHT STEVEN L

    IPC: H01L29/78 ,  H01L21/336 ,  H01L29/165 ,  H01L29/778 ,  H01L21/335 ,  H01L29/76

    Abstract: YO986-100 GERMANIUM CHANNEL SILICON MOSFET An alloy layer comprising germanium and silicon is grown on top of a silicon substrate. The alloy layer is kept thin enough for proper pseudomorphic, dislocation free growth. A layer of silicon is applied to the alloy layer. The initial silicon layer is from two to three times as thick as the alloy layer. Approximately the upper two-thirds of the silicon layer is oxidized, either thermally, anodically or by plasma anodization. The silicon layer that remains between the silicon dioxide and the alloy layer is kept thin enough so that a parasitic channel does not form on the interface between the silicon and the silicon dioxide. The germanium alloyed channel is thus suitably bounded by silicon crystalline structures on both of the channel layer surfaces. The barrier heights between silicon dioxide and silicon are very large thus providing good carrier confinement. A suitably applied voltage will result in a region of high mobility charge carriers at the interface between the alloy layer and the upper silicon layer.

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