公开(公告)号：JP2004207714A

公开(公告)日：2004-07-22

申请号：JP2003413993

申请日：2003-12-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KEVIN K CHAN ,  GUY M COEN ,  IEONG MEIKEI ,  ROY RONNEN A ,  SOLOMON PAUL M ,  YANG MIN

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66484 ,  H01L21/26533 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/7834 ,  H01L29/78648

Abstract: PROBLEM TO BE SOLVED: To provide a dual-gate field effect transistor (DGFET) structure which can noticeably reduce the parasitic capacitance under its source/drain region, and its manufacturing method.
SOLUTION: This double-gate field effect transistor (DGFET) adopts new two means for reducing the parasitic capacitance under its source/drain region. One means is as follows: a silicon region outside a gate is converted into an oxide 44, while a silicon/ledge 46 adjacent to the gate 58 is protected with a first spacer having a first width. This oxidation can be performed easily by means of implantation of self-aligned oxygen ions or other ions. The other means is to have the first spacer removed and replaced with a second spacer 48 which has a width smaller than that of the first one, and a new silicon source/drain region 60 formed under a self-aligned isolation region 56 by lateral selective full overgrowth, by using the newly exposed silicon/ledge 46 as a seed. Thus, the capacitance value of a backplane 32 can be decreased, while the control of the threshold voltage is retained.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2006240898A

公开(公告)日：2006-09-14

申请号：JP2005055790

申请日：2005-03-01

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN JIA ,  ALI AFUZARI-ARUDAKANI ,  KLINKE CHRISTIAN ,  SOLOMON PAUL M ,  AVOURIS PHAEDON

IPC: C01B31/02 ,  H01L21/336 ,  H01L29/06 ,  H01L29/786 ,  H01L51/05

Abstract: PROBLEM TO BE SOLVED: To provide a method for doping carbon nanotube by a solution treatment, a semiconductor device and a method of forming the semiconductor device. SOLUTION: This doping method for carbon nanotube includes a process for exposing the carbon nanotube to a one-electron oxidizer in a solution phase. Further, there are provided a method of forming a carbon nanotube FET device and also a semiconductor device. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 解决的问题：提供一种通过固溶处理掺杂碳纳米管的方法，半导体器件和形成半导体器件的方法。 解决方案：用于碳纳米管的这种掺杂方法包括在溶液相中将碳纳米管暴露于单电子氧化剂的方法。 此外，提供了形成碳纳米管FET器件以及半导体器件的方法。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006332662A

公开(公告)日：2006-12-07

申请号：JP2006142405

申请日：2006-05-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COHEN GUY MOSHE ,  SOLOMON PAUL M

IPC: H01L29/786 ,  H01L21/28 ,  H01L21/336 ,  H01L29/12 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02653 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7828 ,  Y10S977/762 ,  Y10S977/938

Abstract: PROBLEM TO BE SOLVED: To provide a vertical FET including a nanowire channel, with the access resistance to the lower contact reduced and the gate length controlled. SOLUTION: A vertical FET structure, having a nanowire which constitutes a FET channel, is disclosed. A nanowire is formed on a conductive silicide layer. The nanowire is controlled by a gate surrounding it. Upper and lower insulating plugs function as gate spacers and make the gate-source capacitance and the gate-drain capacitance reduced. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种包括纳米线通道的垂直FET，降低对下接触器的访问阻力，并控制栅极长度。 公开了具有构成FET沟道的纳米线的垂直FET结构。 在导电硅化物层上形成纳米线。 纳米线由周围的门控制。 上下绝缘插头用作栅极隔离层，使栅源电容和栅极 - 漏极电容减小。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004207726A

公开(公告)日：2004-07-22

申请号：JP2003421646

申请日：2003-12-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SOLOMON PAUL M ,  KEVIN K CHAN ,  HANAFI HUSSEIN I

IPC: H01L21/76 ,  H01L21/265 ,  H01L21/336 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L29/78648

Abstract: PROBLEM TO BE SOLVED: To provide a dual gate field-effect transistor (DGFET) structure, with a significantly reduced parasitic capacity in the source/drain region and its formation method.
SOLUTION: This dual-gate field-effect transistor reduces the parasitic capacity in the DGFET structure by being provided with a self-aligned isolation region 44. Furthermore, the parasitic capacity of the structure is further reduced, by enabling substantial oxidization to occur at a back gate, which is made possible by coating a silicon contained channel 18.
COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：提供双栅极场效应晶体管（DGFET）结构，其在源极/漏极区域中的显着降低的寄生电容及其形成方法。 解决方案：该双栅极场效应晶体管通过提供自对准隔离区域44来减小DGFET结构中的寄生电容。此外，通过使得能够实质上的氧化到 发生在后门，其通过涂覆含硅通道18而成为可能。（C）2004年，JPO和NCIPI

公开(公告)号：DE3787010T2

公开(公告)日：1994-03-17

申请号：DE3787010

申请日：1987-12-23

Applicant: IBM

Inventor： SOLOMON PAUL M ,  THEIS THOMAS N

IPC: H01L29/205 ,  H01L21/338 ,  H01L29/43 ,  H01L29/778 ,  H01L29/78 ,  H01L29/812 ,  H01L29/64 ,  H01L29/76 ,  H01L29/80

公开(公告)号：DE3787010D1

公开(公告)日：1993-09-16

申请号：DE3787010

申请日：1987-12-23

Applicant: IBM

Inventor： SOLOMON PAUL M ,  THEIS THOMAS N

IPC: H01L29/205 ,  H01L21/338 ,  H01L29/43 ,  H01L29/778 ,  H01L29/78 ,  H01L29/812 ,  H01L29/64 ,  H01L29/76 ,  H01L29/80

公开(公告)号：DE112010003495B4

公开(公告)日：2013-12-12

申请号：DE112010003495

申请日：2010-08-30

Applicant: IBM

Inventor： KARG SIEGFRIED ,  BJOERK MIKAEL T ,  KNOCH JOACHIM ,  RIEL HEIKE ,  RIESS WALTER H ,  SOLOMON PAUL M

IPC: H01L29/68 ,  H01L21/336 ,  H01L29/06 ,  H01L29/739

Abstract: Tunnelfeldeffekttransistor-Struktur mit einem indirekt induzierten Tunnelemitter, welcher das folgende umfasst: einen äußeren Mantel, welcher zumindest teilweise ein längliches Kernelement umgibt, wobei das längliche Kernelement aus einem ersten Halbleitermaterial gebildet ist; eine Isolatorschicht, welche zwischen dem äußeren Mantel und dem Kernelement angeordnet ist; wobei der äußere Mantel an einer Stelle angeordnet ist, die einer Source-Zone der Tunnelfeldeffekttransistor-Struktur entspricht; und einen Source-Kontakt, der den äußeren Mantel mit dem Kernelement kurzschließt; wobei der äußere Mantel so aufgebaut ist, dass er in die Source-Zone des Kernelements eine Ladungsträgerkonzentration einführt, die zum Tunneln in eine Kanalzone der Tunnelfeldeffekttransistor-Struktur während eines EIN-Zustands ausreicht.

公开(公告)号：GB2485495A

公开(公告)日：2012-05-16

申请号：GB201200880

申请日：2010-08-30

Applicant: IBM

Inventor： BJOERK MIKAEL T ,  KARG SIEGFRIED F ,  KNOCH JOACHIM ,  RIEL HEIKE E ,  RIESS WALTER H ,  SOLOMON PAUL M

IPC: H01L29/739 ,  H01L29/06

Abstract: An indirectly induced tunnel emitter for a tunneling field effect transistor (TFET) structure includes an outer sheath that at least partially surrounds an elongated core element, the elongated core element formed from a first semiconductor material; an insulator layer disposed between the outer sheath and the core element; the outer sheath disposed at a location corresponding to a source region of the TFET structure; and a source contact that shorts the outer sheath to the core element; wherein the outer sheath is configured to introduce a carrier concentration in the source region of the core element sufficient for tunneling into a channel region of the TFET structure during an on state.

公开(公告)号：CA1223673A

公开(公告)日：1987-06-30

申请号：CA504661

申请日：1986-03-20

Applicant: IBM

Inventor： SOLOMON PAUL M ,  WRIGHT STEVEN L

IPC: H01L29/812 ,  H01L21/338 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H01L27/095 ,  H01L29/10 ,  H01L29/778 ,  H01L29/76

Abstract: Mode Selection Layer for Semiconductor Device A field effect transistor structure suitable for use in an array of such structures disposed on a common substrate is formed with a source terminal, a drain terminal, and a gate terminal upon an upper surface of a semiconductor chip. The chip includes a first layer and a second layer, the first layer being grown epitaxially upon the second layer. The first layer forms a part of the gate terminal and the second layer includes a charge conduction channel coupling the source terminal and the drain terminal. A pocket layer is disposed in the second layer beneath the terminals of the transistor structure and is doped with either an donor dopant or an acceptor dopant for altering the electric field at the conduction channel to insert electrons or remove electrons therefrom so as to convert an operating mode from either an enhancement mode to a depletion mode or from a depletion mode to an enchancement made. A substrate with a terminal on the backside thereof may be placed contiguous the bottom of said second layer, the back terminal being applied to a negative source of voltage for a transistor structure of n-channel format. The semiconductor material of the chip is a obtained from compounds of elements of the groups III and V of the periodic table.

公开(公告)号：GB2485493A

公开(公告)日：2012-05-16

申请号：GB201200163

申请日：2010-08-04

Applicant: IBM

Inventor： BANGSARUNTIP SARUNYA ,  EDELSTEIN DANIEL C ,  KIM HO-CHEOL ,  KOESTER STEVEN ,  SOLOMON PAUL M ,  HINSBERG WILLIAM

IPC: H01L21/311 ,  H01L21/44 ,  H01L21/768

Abstract: An interconnection between a sublithographic-pitched structure and a lithographic pitched structure is formed. A plurality of conductive lines having a sublithographic pitch may be lithographically patterned and cut along a line at an angle less than 45 degrees from the lengthwise direction of the plurality of conductive lines. Alternately, a copolymer mixed with homopolymer may be placed into a recessed area and self-aligned to form a plurality of conductive lines having a sublithographic pitch in the constant width region and a lithographic dimension between adjacent lines at a trapezoidal region. Yet alternately, a first plurality of conductive lines with the sublithographic pitch and a second plurality of conductive lines with the lithographic pitch may be formed at the same level or at different.