公开(公告)号：JPH1154756A

公开(公告)日：1999-02-26

申请号：JP20405697

申请日：1997-07-30

Applicant: IBM

Inventor： MASSIMO VINCENZO FISCHETTI ,  PATRICIA MAY MOONEY ,  TIWARI SANDIP

IPC: H01L21/762 ,  H01L21/336 ,  H01L21/76 ,  H01L27/08 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To raise the mobility of holes and electrons, by causing a first region of a semiconductor layer to surround a second region nearly, making the first region larger than the initial volume of a substance, causing the second region to receive a compressive stress, taking the regeneration of a valence band off in consequence, and decreasing the band edge mass of a carrier such as a hole and so forth. SOLUTION: By oxidation of a peripheral region to be protected by a mask 116, a silicon dioxide surrounding silicon below the mask 116 expands. A layer 114 not being protected is perfectly oxidized and an oxide layer 118 is formed, and a silicon region 119 remains from the layer 114. The mask 116 remains on the silicon region 119. The expansion of volume of the silicon dioxide is slightly larger than the factor of 2, and the molecular weight of the silicon amounts to 12.056 cm . By this expansion, a compressive stress is generated in the silicon region 119 between them. It is possible to form an element such as a p-channel field-effect transistor, etc., on the silicon region 119, following exfoliation of the mask 116. Hole mobility is improved by the compression stress.

公开(公告)号：JP2000323670A

公开(公告)日：2000-11-24

申请号：JP2000077995

申请日：2000-03-21

Applicant: IBM

Inventor： TIWARI SANDIP

IPC: H01L21/8247 ,  G11C11/22 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To obtain a back-plane ferroelectric memory apparatus employing a read transistor, a write transistor and a ferroelectric capacitor storage means. SOLUTION: A back plane 26 forms a gate region underneath the read transistor 20 with the potential of the back plane affected by polarization of the ferroelectric capacitor. The write transistor 18 and the read transistor 20 are different, the write transistor 18 may be a vertical structure and the read transistor 20 may be a back plane planer structure. The drain of the write transistor 18 is connected to the back plane of the read transistor 20 and a plate of the ferroelectric capacitor 22.

公开(公告)号：DE3783162D1

公开(公告)日：1993-02-04

申请号：DE3783162

申请日：1987-05-26

Applicant: IBM

Inventor： JACKSON THOMAS NELSON ,  MURAKAMI MASANORI ,  PRICE WILLIAM HENRY ,  TIWARI SANDIP ,  WOODALL JERRY MAC PHERSON ,  WRIGHT STEVEN LORENZ

IPC: H01L21/20 ,  H01L21/28 ,  H01L29/43 ,  H01L29/45 ,  H01L29/40 ,  H01L29/20

公开(公告)号：DE3474610D1

公开(公告)日：1988-11-17

申请号：DE3474610

申请日：1984-06-08

Applicant: IBM

Inventor： RUPPRECHT HANS STEPHAN ,  TIWARI SANDIP

IPC: H01L29/43 ,  H01L21/28 ,  H01L21/285 ,  H01L29/45 ,  H01L21/40

公开(公告)号：DE3783162T2

公开(公告)日：1993-07-01

申请号：DE3783162

申请日：1987-05-26

Applicant: IBM

Inventor： JACKSON THOMAS NELSON ,  MURAKAMI MASANORI ,  PRICE WILLIAM HENRY ,  TIWARI SANDIP ,  WOODALL JERRY MAC PHERSON ,  WRIGHT STEVEN LORENZ

IPC: H01L21/20 ,  H01L21/28 ,  H01L29/43 ,  H01L29/45 ,  H01L29/40 ,  H01L29/20

公开(公告)号：CA1308818C

公开(公告)日：1992-10-13

申请号：CA597294

申请日：1989-04-20

Applicant: IBM

Inventor： BATEY JOHN ,  TIWARI SANDIP ,  WRIGHT STEVEN L

IPC: H01L29/78 ,  H01L21/203 ,  H01L21/205 ,  H01L21/28 ,  H01L21/31 ,  H01L21/314 ,  H01L21/336 ,  H01L29/267 ,  H01L29/43 ,  H01L29/60

Abstract: UNPINNED OXIDE-COMPOUND SEMICONDUCTOR STRUCTURES AND METHOD OF FORMING SAME Unpinned epitaxial metal-oxide-compound semiconductor structures are disclosed and a method of fabricating such structures is described. Epitaxial layers of compound semiconductor are grown by MBE which result in the formation of a smooth surface having a stabilized reconstruction. An elemental semiconductor layer is deposited epitaxially in situ with the compound semiconductor layer which unpins the surface Fermi level. A layer of insulator material is then deposited on the elemental semiconductor layer by PECVD. In one embodiment, the compound semiconductor is GaAs and the elemental semiconductor is Si. The insulator material is a layer of high quality SiO2. A metal gate is deposited on the SiO2 layer to form an MOS device. The epitaxial GaAs layer has a density of states which permits the interface Fermi level to be moved through the entire forbidden energy gap. In another embodiment, the SiO2 deposition completely consumes the interface Si layer so that the resulting MOS device comprises SiO2 directly overlying the GaAs layer. Y0988-028

公开(公告)号：DE3579379D1

公开(公告)日：1990-10-04

申请号：DE3579379

申请日：1985-06-19

Applicant: IBM

Inventor： TIWARI SANDIP

IPC: H01L21/225 ,  H01L21/324 ,  H01L21/338 ,  H01L29/04 ,  H01L29/812 ,  H01L29/80

Abstract: A method of producing a FET in a gallium arsenide substrate comprises forming a gate (2) on a [100] surface of the gallium arsenide substrate in the [011] orientation, ion implanting active impurities to form FET source (5) and drain (6) regions which are self-aligned with respect to the gate (2), and annealing the structure subsequently to the ion implanting to cause the active impurities to diffuse laterally and thereby form a channel region beneath the gate (2).

公开(公告)号：DE68926591T2

公开(公告)日：1996-11-28

申请号：DE68926591

申请日：1989-03-06

Applicant: IBM

Inventor： BATEY JOHN ,  TIWARI SANDIP ,  WRIGHT STEVEN LORENZ

IPC: H01L29/78 ,  H01L21/203 ,  H01L21/205 ,  H01L21/28 ,  H01L21/31 ,  H01L21/314 ,  H01L21/336 ,  H01L29/267 ,  H01L29/43 ,  H01L29/41

Abstract: Unpinned metal-oxide-compound semiconductor structures are disclosed and a method of fabricating such structures is described. Epitaxial layers of compound semiconductor (14) are grown by MBE which results in the formation of a smooth surface having a stabilized reconstruction. An elemental semiconductor layer (16) is deposited epitaxially in situ with the compound semiconductor layer (14) which unpins the surface Fermi level. A layer of insulator material (18) is then deposited on the elemental semiconductor layer (16) by PECVD. In one embodiment, the compound semiconductor (14) is GaAs and the elemental semiconductor (16) is Si. The insulator material (18) is a layer of high quality SiO2. A metal gate (20) is deposited on the SiO2 layer (18) to form a MOS device (13). The epitaxial GaAs layer (14) has a density of states which permits the interface Fermi level to be moved through the entire forbidden energy gap. In another embodiment, the SiO2 deposition completely consumes the interface Si layer (16) so that the resulting MOS device comprises SiO2 (18) directly overlying the GaAs layer (14).

公开(公告)号：DE68926591D1

公开(公告)日：1996-07-11

申请号：DE68926591

申请日：1989-03-06

Applicant: IBM

Inventor： BATEY JOHN ,  TIWARI SANDIP ,  WRIGHT STEVEN LORENZ

IPC: H01L29/78 ,  H01L21/203 ,  H01L21/205 ,  H01L21/28 ,  H01L21/31 ,  H01L21/314 ,  H01L21/336 ,  H01L29/267 ,  H01L29/43 ,  H01L29/41

Abstract: Unpinned metal-oxide-compound semiconductor structures are disclosed and a method of fabricating such structures is described. Epitaxial layers of compound semiconductor (14) are grown by MBE which results in the formation of a smooth surface having a stabilized reconstruction. An elemental semiconductor layer (16) is deposited epitaxially in situ with the compound semiconductor layer (14) which unpins the surface Fermi level. A layer of insulator material (18) is then deposited on the elemental semiconductor layer (16) by PECVD. In one embodiment, the compound semiconductor (14) is GaAs and the elemental semiconductor (16) is Si. The insulator material (18) is a layer of high quality SiO2. A metal gate (20) is deposited on the SiO2 layer (18) to form a MOS device (13). The epitaxial GaAs layer (14) has a density of states which permits the interface Fermi level to be moved through the entire forbidden energy gap. In another embodiment, the SiO2 deposition completely consumes the interface Si layer (16) so that the resulting MOS device comprises SiO2 (18) directly overlying the GaAs layer (14).

公开(公告)号：DE3574529D1

公开(公告)日：1990-01-04

申请号：DE3574529

申请日：1985-04-11

Applicant: IBM

Inventor： TIWARI SANDIP

IPC: H01L29/205 ,  H01L21/331 ,  H01L29/20 ,  H01L29/423 ,  H01L29/45 ,  H01L29/47 ,  H01L29/73 ,  H01L29/732 ,  H01L29/737 ,  H01L29/60 ,  H01L29/72

Abstract: The base region (4) and the collector region (6) of a heterojunction transistor, and an electrode (8) bridging the base and collector regions, are formed of such materials that the electrode (8) forms an ohmic contact with the base region (4) and a Schottky barrier contact with the collector region (6). The transistor may have a p-type GaAlAs base region and an n-type GaAs collector region and the electrode (8) may comprise platinum, palladium or nickel. … Alternatively, a bridging electrode makes an ohmic contact to the base region and a Schottky barrier contact to the emitter region.