公开(公告)号：JP2001024513A

公开(公告)日：2001-01-26

申请号：JP2000171485

申请日：2000-06-08

Applicant: IBM

Inventor： GOLDRIAN GOTTFRIED ANDREAS ,  ZILLES GERHARD

IPC: H03M5/12 ,  H03D3/00 ,  H04B14/04 ,  H04L7/02 ,  H04L7/033 ,  H04L27/156

Abstract: PROBLEM TO BE SOLVED: To obtain a method and a device capable of simply substituting a circuit realized by miniaturized digital logic for a PLL circuit. SOLUTION: In order to measure a pulse interval for encoding data information by utilizing a high frequency signal always existing in a current system as a logic clock independent of a coded data signal, an edge detector 10 generates an edge pulse when the coded signal is transited. A time counter 12 counts the cycle of logic clocks between two succeeding edge pulses. A window comparator 16 compares a prescribed counting range with the cycle count value and generates time result signals 1t, 2t, 3t, >3t, etc. A decoder state machine 20 samples a time result at each edge pulse and activates a decoded data bit (0 or 1), a data clock frame start signal or NO signal.

公开(公告)号：GB2352373B

公开(公告)日：2004-02-18

申请号：GB0013321

申请日：2000-06-02

Applicant: IBM

Inventor： GOLDRIAN GOTTFRIED ANDREAS ,  ZILLES GERHARD

IPC: H03M5/12 ,  H03D3/00 ,  H04B14/04 ,  H04L7/02 ,  H04L7/033 ,  H04L27/156

公开(公告)号：GB2352373A

公开(公告)日：2001-01-24

申请号：GB0013321

申请日：2000-06-02

Applicant: IBM

Inventor： GOLDRIAN GOTTFRIED ANDREAS ,  ZILLES GERHARD

IPC: H03M5/12 ,  H03D3/00 ,  H04B14/04 ,  H04L7/02 ,  H04L7/033 ,  H04L27/156

Abstract: The present invention demodulates a coded signal, such as a frequency modulated (FM) signal by measuring the duration of pulses of the coded signal using a high frequency logic clock signal. An edge detector (100, Fig. 2) generates an edge pulse whenever a transition in the coded signal occurs. A time counter (12, Fig. 2) counts the cycles of the high frequency logic clock between the occurrence of two subsequent edge pulses. Then a window comparator (16, Fig. 2) compares the cycle counts with predefined count ranges and generates the time result signal, e.g. 1t, 2t, 3t or >3t. A decoder state machine (20, Fig. 2) post-connected to said comparator samples the time results at every edge pulse, generates a data clock with the decoded data bit (0 or 1) and indicates a frame start signal. The present invention provides demodulation apparatus which is less expensive than a PLL.

公开(公告)号：GB2466222B

公开(公告)日：2013-11-13

申请号：GB0822763

申请日：2008-12-15

Applicant: IBM

Inventor： KLEIN MATTHIAS ,  ZILLES GERHARD ,  WALZ MANFRED ,  GENTNER THOMAS ,  WAGNER ANDREAS ,  KOENIG ANDREAS

IPC: G06F9/50 ,  G06F11/07 ,  G06F13/20 ,  H04L12/841

公开(公告)号：GB2466222A

公开(公告)日：2010-06-16

申请号：GB0822763

申请日：2008-12-15

Applicant: IBM

Inventor： KLEIN MATTHIAS ,  ZILLES GERHARD ,  WALZ MANFRED ,  GENTNER THOMAS ,  WAGNER ANDREAS ,  KOENIG ANDREAS

IPC: G06F11/00 ,  G06F9/50 ,  G06F13/20 ,  H04L12/56

Abstract: Disclosed is a system for managing the resources processing data transfers in a transaction based input/output chip of a computer system. A transaction is associated with a resource, 18 the transaction being a request packet and a corresponding response packet. The system has a transaction table 10 for holding one resource for each request until the resource has been processed and a resource management 12 for storing information about the availability of these resources, which has become available before a predetermined timeout period T has been exceeded. The system has a FIFO (first-in first-out) memory 14 for buffering those resources, which have been made available after the first timeout period and a second timeout period Q have been exceeded. An arbiter circuit 16 for chooses the resources from the resource management, if any are available, if not the timed-out resources from the FIFO memory are used.