公开(公告)号：DE10351030A1

公开(公告)日：2005-06-09

申请号：DE10351030

申请日：2003-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  FREY ULRICH ,  FISCHER BJOERN

IPC: H01L21/336 ,  H01L21/8242 ,  H01L29/423 ,  H01L29/78 ,  H01L27/108 ,  G11C11/40

Abstract: Transistor structures, with one source/drain region connected to a charge storage device to be insulated includes an asymmetric gate conductor structure. At a first side wall, which faces the one source/drain region, the asymmetric gate conductor structure has a side wall oxide with a greater thickness and a bird's beak structure with a greater length than at an opposite, second side wall. An effective channel length is increased for the same feature size of the gate conductor structure. Memory cells can be realized in a higher density.

公开(公告)号：DE10342028A1

公开(公告)日：2004-03-25

申请号：DE10342028

申请日：2003-09-11

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHIDAMBARRAO DURESETI ,  FREY ULRICH ,  HEDGE SURYANARAYAN ,  TONTI WILLIAM

IPC: H01L21/82 ,  H01L23/525 ,  H01L27/10 ,  H01L21/768

Abstract: An integrated circuit is manufactured by doping portion of semiconductor substrate with nitrogen and a charge carrier dopant source, forming a thin dielectric on the doped portion of the substrate, forming a first separated from the substrate by the thin dielectric, and forming a second conductor coupled to the doped portion of the substrate. The thin dielectric is subjected to breakdown upon application of a breakdown voltage. An Independent claim is also included for an integrated circuit including an anti-fuse.

公开(公告)号：DE102004005992B3

公开(公告)日：2005-11-17

申请号：DE102004005992

申请日：2004-02-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREY ULRICH ,  GOLDBACH MATTHIAS ,  OFFENBERG DIRK

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8239 ,  H01L27/085 ,  H01L27/105 ,  H01L29/49 ,  H01L29/739 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

Abstract: The present invention provides a fabrication method for a semiconductor structure and a corresponding semiconductor structure. The fabrication method comprises the following steps: provision of a semiconductor substrate ( 1 ) with a gate dielectric ( 5 ); provision of a plurality of multilayered, elongate gate stacks (GS 1; GS 2 ) which essentially run parallel to one another on the gate dielectric ( 5 ), which gate stacks have a bottommost layer ( 10 ) made of silicon; provision of a first liner layer ( 60 ) made of a first material over the gate stacks (GS 1; GS 2 ) and the gate dielectric ( 5 ) uncovered beside the latter, the thickness (h) of which liner layer is less than a thickness (h') of the bottommost layer ( 10 ) made of silicon; provision of sidewall spacers ( 70 ) made of a second material on the vertical sidewalls of the gate stacks (GS 1; GS 2 ) over the first liner layer ( 60 ), a region of the first liner layer ( 60 ) over the gate dielectric ( 5 ) between the gate stacks (GS 1; GS 2 ) remaining free; selective removal of the first liner layer ( 60 ) with respect to the sidewall spacers ( 70 ) for the purpose of laterally uncovering the bottommost layer ( 10 ) made of silicon of the gate stacks (GS 1; GS 2 ); and selective oxidation of the uncovered bottommost layer ( 10 ) for the purpose of forming sidewall oxide regions ( 50 ') on the gate stacks (GS 1; GS 2 ).

公开(公告)号：DE10332312B3

公开(公告)日：2005-01-20

申请号：DE10332312

申请日：2003-07-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREY ULRICH ,  LINDOLF JUERGEN ,  FELBER ANDREAS

IPC: H01L23/525

Abstract: The integrated semiconductor circuit (20) has a programmable switch element (10) switched between an off state and an on state by supplying a positive programming voltage (V+) to a counter-electrode (5) of the switch element, separated from a substrate electrode (2) within a substrate (1) held at a substrate potential (Vo) via an insulation layer (8). The substrate electrode is supplied with a negative programming voltage (V-) during programming of the switch element, a current barrier layer (7) preventing a current flow between the substrate electrode and the substrate.

公开(公告)号：DE102004004596A1

公开(公告)日：2004-09-09

申请号：DE102004004596

申请日：2004-01-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHMANN GUNTER ,  FREY ULRICH

IPC: G11C17/16 ,  H01L23/525 ,  H01L27/112 ,  H02H9/00

公开(公告)号：DE10342028B4

公开(公告)日：2016-04-07

申请号：DE10342028

申请日：2003-09-11

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHIDAMBARRAO DURESETI ,  FREY ULRICH ,  HEDGE SURYANARAYAN ,  TONTI WILLIAM

IPC: H01L21/82 ,  H01L23/525 ,  H01L21/768 ,  H01L27/10

Abstract: Verfahren zum Ausbilden einer integrierten Schaltung, mit einer Antifuse auf einem Halbleitersubstrat, umfassend: Dotieren einer dotierten Wanne (30) eines Halbleitersubstrats (14) mit Stickstoff und einem Ladungsträger-Dotierstoff vom Ladungsträgertyp der dotierten Wanne, um einen Dotierbereich (28) zu erzeugen, wobei beim Dotieren ein Verhältnis des Ladungsträger-Dotierstoffs zum Stickstoff zwischen ca. 0,5:1 und 1,3:1 verwendet wird; Ausbilden eines dünnen Dielektrikums (16) auf dem Dotierbereich (28) des Halbleitersubstrats; Ausbilden eines durch das dünne Dielektrikum von dem Halbleitersubstrat getrennten ersten Leiters (12); Ausbilden eines leitend an den Dotierbereich (28) des Halbleitersubstrats gekoppelten zweiten Leiters (24), wobei an dem dünnen Dielektrikum (16) bei Anlegen einer Durchbruchsspannung ein Durchbruch auftritt.

公开(公告)号：DE10107666C1

公开(公告)日：2002-08-14

申请号：DE10107666

申请日：2001-02-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AYADI KAMEL ,  MUELLER JOCHEN ,  LINDOLF JUERGEN ,  SAVIGNAC DOMINIQUE ,  DANKOWSKI STEFAN ,  LEHR MATTHIAS UWE ,  BRINTZINGER AXEL ,  FREY ULRICH

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/522

Abstract: The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a circuit substrate (1); providing a metallization region (10a) comprising a first metal in the circuit substrate (1); providing a first insulation layer (25) above the metallization region (10a); forming an opening (13) in the insulating layer (25) in order to uncover at least part of the surface of the metallization region (10a); depositing a functional layer (15') above the resulting structure; depositing a second insulating layer (35) above the resulting structure, in such a manner that the opening (13) is filled; polishing-back of the second insulating layer (35) and of the functional layer (15') in order to uncover the surface of the first insulating layer (25); forming a contact (11a') in the second insulating layer (35) inside the opening (13) in order to make contact with the functional layer (15'); and providing an interconnect (40a) for electrical connection of the contact (11a').

公开(公告)号：DE10258780A1

公开(公告)日：2003-07-10

申请号：DE10258780

申请日：2002-12-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREY ULRICH ,  LEHMANN GUNTHER ,  WEINFURTNER OLIVER

IPC: G11C17/18 ,  H03K17/00

Abstract: An anti-fuse system composed of a multiplicity of anti-fuse circuits (24, 26, 28, N) connected across a voltage source (10) by a pair of conductors (16, 18). Each anti-fuse circuit comprising an anti-fuse (30) connected in a series with a blow or control transistor (36) and a control circuit (44) for monitoring the status of the anti-fuse (30), Control circuit (44) provides an "on" signal to the gate (38) of control transistor (36) only when a_"select_" signal is received at an input (46) of control circuit (44) and if anti-fuse (30) has not been blown. After the anti-fuse (30) is blown, control circuit (44) turns off the control transistor (36) thereby providing a constant power source voltage across each anti-fuse circuit (24, 26, 28, N) regardless of the number of parallel anti-fuses which have been blown.