公开(公告)号：JP2001044390A

公开(公告)日：2001-02-16

申请号：JP2000209997

申请日：2000-07-11

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BRONNER GARY ,  GRUENING ULRIKE ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To obtain non-planar type transistor structure by arranging an active transistor device partially on the sidewall of a deep trench in a cell, and aligning the side wall to a first crystal plane with a crystal orientation along the single- crystal axis. SOLUTION: A deep trench accumulation capacitor 10 is formed in a pad 22 and a substrate 24, and a pattern is formed on the pad 22 using a light lithography step. Then, using such a dry etching step as reactive ion etching, a trench 20 is formed to a desired depth in the substrate 24 through the pad 22. Then, an active transistor device is partially provided on a sidewall 32 of the trench 20, and the sidewall 32 is aligned to first crystal planes (001) and (011) with a crystal orientation set along the single-crystal axis.

公开(公告)号：WO0245134A3

公开(公告)日：2003-04-03

申请号：PCT/US0151214

申请日：2001-11-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  WEYBRIGHT MARY E ,  HORN PETER ,  BRONNER GARY ,  CONTI RICHARD A ,  SCHROEDER UWE ,  GAMBINO JEFFREY PETER

IPC: H01L21/60 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L21/76897 ,  H01L21/823456 ,  H01L27/1052 ,  H01L27/10873

Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

Abstract translation: 在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。 在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。 这些介质间隔物允许使阵列栅极导体抗蚀剂线小于最终的栅极导体线宽。 这扩大了阵列栅极导体处理窗口。 第二电介质盖层改善了支撑装置和阵列装置的线宽控制。 在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。 阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。 在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。

公开(公告)号：DE60133214D1

公开(公告)日：2008-04-24

申请号：DE60133214

申请日：2001-11-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  WEYBRIGHT MARY E ,  HOH PETER ,  BRONNER GARY ,  CONTI RICHARD A ,  SCHROEDER UWE ,  GAMBINO JEFFREY PETER

IPC: H01L21/8242 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8239

Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

公开(公告)号：JPH11163302A

公开(公告)日：1999-06-18

申请号：JP27902398

申请日：1998-09-30

Applicant: SIEMENS AG ,  IBM

Inventor： GAMBINO JEFFREY P ,  ALSMEIER JOHANN ,  BRONNER GARY

IPC: H01L27/108 ,  H01L21/76 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To respond effectively and readily to contradictory requests chip regions by separating a first region from a second region by means of an insulation region. SOLUTION: A substrate 101 comprises at least a part of first and second regions 110, 130. An insulation region 150 is a shallow trench insulator(STI) comprising a dielectric material, such as oxide. The second region is an array region of a DRAMIC. An insulation region such as an STI is provided for separating a trench capacitor, for example. A region is provided by a well of dopant for a device to be formed next. Various layers forming a gate stack of a device are formed on the surface of a substrate. The process includes the formation of an oxide layer 160 through thermal oxidation, for example. The oxide layer 160 is used as a gate oxide. The gate layer 161 is deposited on a gate oxide. The gate layer 161 is a composite layer such as polycide.

公开(公告)号：JP2000228442A

公开(公告)日：2000-08-15

申请号：JP2000025509

申请日：2000-02-02

Applicant: IBM ,  SIEMENS AG

Inventor： HO HERBERT ,  SRINIVASAN RADHIKA ,  HAMMERL ERWIN ,  AGAHI FARID ,  BRONNER GARY ,  FLIETNER BERTRAND

IPC: H01L21/76 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To reduce parasitic leak of a shallow trench isolation via. SOLUTION: A distance between a silicon nitride liner 43 and an active silicon sidewall is increased by depositing an insulation oxide layer 20 prior to depositing of the silicon nitride liner 43. Preferably, the insulation oxide layer 20 comprises tetraethyl orthosilicate. The method includes formation of one or a plurality of shallow trench isolations inside a semiconductor wafer through etching, sticking of an insulation oxide layer 20 inside a trench, formation of thermal oxide 25 inside a trench and sticking of the silicon nitride liner 43 inside a trench. The thermal oxide 25 can be formed before or after the insulation oxide layer 20 is deposited.

公开(公告)号：JPH11330402A

公开(公告)日：1999-11-30

申请号：JP9246899

申请日：1999-03-31

Applicant: SIEMENS AG ,  IBM

Inventor： GRUENING ULRIKE ,  JAIPRAKASH VENKATACHALAM C ,  BRONNER GARY ,  RADENS CARL ,  BEINTNER JOCHEN

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To reduce the diffusion of the height of an embedded strap by making the depression extending below the surface of the substrate in a filling material, to determine the top surface of a buried strap and by making a recess extending below the top surface of the embedded strap in a collar to determine the bottom side surface. SOLUTION: A substrate includes a partially completed trench capacitor. A collar 110 is made on the upper portion of the trench capacitor. A trench 108 is filled with a filling material 112 and the inner sidewall of the collar is lined with the filling material 112. A recess having a predetermined depth is made in the filling material 112. The depth of the recess actually determines the top portion of an embedded strap. A hole is made in the collar to the depth of 120 below the top surface 118 of the filling material 112. A layer 122 is removed from the side of the trench 108 and the top surface of a semiconductor device 100, while a recessed region 124 filled with the material of the layer 122 is left.

公开(公告)号：JP2000133788A

公开(公告)日：2000-05-12

申请号：JP21479399

申请日：1999-07-29

Applicant: IBM ,  SIEMENS AG

Inventor： ALSMEIER JOHANN ,  BRONNER GARY ,  KAPLITA GEORGE A ,  KLEINHENZ RICHARD ,  MULLER PAUL K ,  RANADE RAJIV M ,  ROITHNER KLAUS

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obviate the need for etching redesigning by laying out a deep trench pattern by using a dummy semiconductor material loading rate, that is obtained by subtracting a device trench level semiconductor material loading rate from an estimated final trench level semiconductor material loading rate. SOLUTION: First, a final chip design silicon loading rate is estimated, and a plurality of device deep trenche patterns are laid out, that constitute an integrated circuit chip 14 to be developed. These trenches cumulatively have device silicon loading rates. Next, the device silicon loading rate is subtracted from the the estimated final chip design loading rate so as to compute a dummy silicon loading rate, and cumulative silicon loading rates are used to lay out a plurality of dummy deep trenches 22. It is preferable have the device trenches disperse uniformly and the dummy trenches over a chip.

公开(公告)号：DE60133214T2

公开(公告)日：2009-04-23

申请号：DE60133214

申请日：2001-11-13

Applicant: IBM ,  QIMONDA AG

Inventor： DIVAKARUNI RAMACHANDRA ,  WEYBRIGHT MARY E ,  HOH PETER ,  BRONNER GARY ,  CONTI RICHARD A ,  SCHROEDER UWE ,  GAMBINO JEFFREY PETER

IPC: H01L21/8242 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8239

Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

公开(公告)号：AT518240T

公开(公告)日：2011-08-15

申请号：AT00101726

申请日：2000-01-27

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： HO HERBERT ,  SRINIVASAN RADHIKA ,  HAMMERL ERWIN ,  AGAHI FARID ,  BRONNER GARY ,  FLIETNER BERTRAND

IPC: H01L21/76 ,  H01L21/762

Abstract: A reduction in parasitic leakages of shallow trench isolation vias is disclosed wherein the distance between the silicon nitride liner and the active silicon sidewalls is increased by depositing an insulating oxide layer prior to deposition of the silicon nitride liner. Preferably, the insulating oxide layer comprises tetraethylorthosilicate. The method comprises of etching one or more shallow trench isolations into a semiconductor wafer; depositing an insulating oxide layer into the trench; growing a thermal oxide in the trench; and depositing a silicon nitride liner in the trench. The thermal oxide may be grown prior to or after deposition of the insulating oxide layer.