公开(公告)号：HK1035436A1

公开(公告)日：2001-11-23

申请号：HK01104466

申请日：2001-06-28

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BRINTZINGER AXEL ,  KIEWRA EDWARD W ,  NARAYAN CHANDRASEKHAR ,  RADENS CARL J

IPC: H01L21/82 ,  G11C29/04 ,  H01H85/00 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/02 ,  H01L27/108 ,  H01L ,  G11C

Abstract: An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.

公开(公告)号：JP2005197743A

公开(公告)日：2005-07-21

申请号：JP2005000921

申请日：2005-01-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CASEY JON A ,  FERRANTE WILLIAM J ,  KIEWRA EDWARD W ,  RADENS CARL J ,  TONTI WILLIAM R

IPC: H01L21/28 ,  G01K7/22 ,  H01C7/00 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04

CPC classification number: H01L21/76895 ,  G01K7/226 ,  H01C7/006 ,  H01L21/76224 ,  H01L21/76838

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for forming a thermistor.
SOLUTION: An isolation region is formed in a substrate including at least an upper side layer of a single crystal semiconductor. A salicide precursor layer is formed on the isolation region and the upper side layer. Then, reaction of the salicide precursor and the upper side layer is performed and a salicide which is self-aligned to the upper side layer is formed. Finally, no reaction portion of the salicide precursor is removed, while preserving the portion of the salicide precursor on the isolation region as the main body of the thermistor. In alternative method, an integrated circuit thermistor is formed from a thermistor material region in an embossed region of interlayer dielectric (ILD).
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于形成热敏电阻的结构和方法。 解决方案：在至少包含单晶半导体的上侧层的衬底中形成隔离区。 在隔离区域和上侧层上形成自对准硅化物前体层。 然后，进行自对准硅化物前体与上侧层的反应，形成与上侧层自对准的自对准硅化物。 最后，除去自杀化合物前体的反应部分，同时保留作为热敏电阻的主体的隔离区上的部分自杀化合物前体。 在替代方法中，集成电路热敏电阻由层间电介质（ILD）的压花区域中的热敏电阻材料区域形成。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2007149581A3

公开(公告)日：2008-08-28

申请号：PCT/US2007014684

申请日：2007-06-25

Applicant: IBM ,  KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

Inventor： KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

IPC: H01L21/336

CPC classification number: H01L29/7787 ,  H01L29/66462

Abstract: A semiconductor-containing heterostructure including, from bottom to top, a IH-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a HI-V compound semiconductor barrier layer, and an optional, yet preferred, IH-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The HI-V compound semiconductor buffer layer and the HI-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the pi-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

Abstract translation: 一种含半导体的异质结构，包括从底部到顶部的IH-V化合物半导体缓冲层，III-V族化合物半导体沟道层，HI-V族化合物半导体阻挡层和任选的，但优选的IH-V化合物 提供半导体盖层。 阻挡层可以是掺杂的，或者优选地是未掺杂的。 HI-V化合物半导体缓冲层和HI-V化合物半导体阻挡层由具有比p-V化合物半导体沟道层的带隙更宽的带隙的材料构成。 由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，载流子在特定栅极偏置范围内被限制在沟道层上。 本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。

公开(公告)号：WO2007149581A2

公开(公告)日：2007-12-27

申请号：PCT/US2007014684

申请日：2007-06-25

Applicant: IBM ,  KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

Inventor： KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

IPC: H01L21/336 ,  H01L29/778

CPC classification number: H01L29/7787 ,  H01L29/66462

Abstract: A semiconductor-containing heterostructure including, from bottom to top, a IH-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a HI-V compound semiconductor barrier layer, and an optional, yet preferred, IH-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The HI-V compound semiconductor buffer layer and the HI-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the pi-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

Abstract translation: 含半导体的异质结构包括从下至上的IH-V化合物半导体缓冲层，III-V族化合物半导体沟道层，HI-V族化合物半导体阻挡层和任选的，但优选的IH-V化合物 提供半导体盖层。 阻挡层可以是掺杂的，或者优选地是未掺杂的。 HI-V化合物半导体缓冲层和HI-V化合物半导体阻挡层由具有比p-V化合物半导体沟道层的带隙更宽的带隙的材料构成。 由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，所以载流子在特定栅极偏置范围内被限制在沟道层。 本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。

公开(公告)号：JP2000252364A

公开(公告)日：2000-09-14

申请号：JP2000047093

申请日：2000-02-24

Applicant: IBM ,  SIEMENS AG

Inventor： BRINTZINGER AXEL ,  KIEWRA EDWARD W ,  NARAYAN CHANDRASEKHAR ,  KAARU JIEI RADENSU

IPC: H01L21/82 ,  G11C29/04 ,  H01H85/00 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/02 ,  H01L27/108 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a fuse link structure which reduces the magnitude of damage which is caused when a fuse element is blown and to provide its method. SOLUTION: This integrated circuit is provided with a main element 102. The integrated circuit is provided with a redundant element 104 which is replaced selectively with the main element 102 by at lease one fuse. The fuse contains a first layer 401 which comprises at least one fuse link region 402, contains a second layer 401 on the first layer, a gap 410 inside the second layer on the fuse link region 402, and contains a fuse window 408 in a dielectric layer 407. Since the gap 410 guides energy and a fuse material to the fuse window 408 from the fuse link region 402, it is possible to reduce damage to a circumferential structure.

公开(公告)号：JPH11154739A

公开(公告)日：1999-06-08

申请号：JP25842598

申请日：1998-09-11

Applicant: SIEMENS AG ,  IBM

Inventor： WEIGAND PETER ,  KIEWRA EDWARD W ,  NARAYAN CHANDRASEKHAR ,  ARNDT KENNETH C ,  LACHTRUPP DAVID ,  GILMOUR RICHARD ALFRED ,  PALAGONIA ANTHONY MICHAEL

IPC: H01L21/82 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To minimize damage to a substrate being subjected to fuse operation and to reduce the fuse pitch, by arranging a screening part where a laser fuse link is set by laser beams so that the damage of laser induction from laser beams is minimized at a region below the screening part. SOLUTION: A dynamic access memory integrated circuit has a plurality of screening parts 402, 404, 406, and 408 located on the lower side of laser fuse links 202, 204, 206, and 208. The screening parts are constituted so that a first regions located on the lower side of the screening parts can be essentially minimized when the first laser fuse links are set by laser beams. The screening part is formed by a material for reflecting nearly entire laser energy applied the screening part. A reflection material such as tungsten, molybdenum, platinum, chromium, titanium, and their alloys operates favorably.

公开(公告)号：DE69626562D1

公开(公告)日：2003-04-17

申请号：DE69626562

申请日：1996-04-11

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： ECKSTEIN ELKE ,  HOFFMAN BIRGIT ,  KIEWRA EDWARD W ,  KOCON WALDEMAR WALTER ,  WEISS MARK JAY

IPC: C23F4/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/321 ,  H01L21/311

Abstract: A back end of the line dry etch method is disclosed. Etching of a mask oxide and temporary (sacrificial) silicon mandrel occurs following the formation of gate stacks and tungsten studs. The mask oxide is etched selectively to tungsten and silicon through the use of a polymerizing oxide etch. The silicon is etched selectively to both silicon nitride, silicon oxide, and tungsten. The process removes the silicon mandrel and associated silicon residual stringers by removing backside helium cooling, while using HBr as the single species etchant, and by adjusting the duration, the pressure, and the electrode gaps during the silicon etch process. The silicon may be undoped polysilicon, doped polysilicon, or single crystal silicon.

公开(公告)号：DE69626562T2

公开(公告)日：2004-02-19

申请号：DE69626562

申请日：1996-04-11

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： ECKSTEIN ELKE ,  HOFFMAN BIRGIT ,  KIEWRA EDWARD W ,  KOCON WALDEMAR WALTER ,  WEISS MARK JAY

IPC: C23F4/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/321 ,  H01L21/311

Abstract: A back end of the line dry etch method is disclosed. Etching of a mask oxide and temporary (sacrificial) silicon mandrel occurs following the formation of gate stacks and tungsten studs. The mask oxide is etched selectively to tungsten and silicon through the use of a polymerizing oxide etch. The silicon is etched selectively to both silicon nitride, silicon oxide, and tungsten. The process removes the silicon mandrel and associated silicon residual stringers by removing backside helium cooling, while using HBr as the single species etchant, and by adjusting the duration, the pressure, and the electrode gaps during the silicon etch process. The silicon may be undoped polysilicon, doped polysilicon, or single crystal silicon.

公开(公告)号：AT234508T

公开(公告)日：2003-03-15

申请号：AT96105741

申请日：1996-04-11

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： ECKSTEIN ELKE ,  HOFFMAN BIRGIT ,  KIEWRA EDWARD W ,  KOCON WALDEMAR WALTER ,  WEISS MARK JAY

IPC: C23F4/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/321 ,  H01L21/311

Abstract: A back end of the line dry etch method is disclosed. Etching of a mask oxide and temporary (sacrificial) silicon mandrel occurs following the formation of gate stacks and tungsten studs. The mask oxide is etched selectively to tungsten and silicon through the use of a polymerizing oxide etch. The silicon is etched selectively to both silicon nitride, silicon oxide, and tungsten. The process removes the silicon mandrel and associated silicon residual stringers by removing backside helium cooling, while using HBr as the single species etchant, and by adjusting the duration, the pressure, and the electrode gaps during the silicon etch process. The silicon may be undoped polysilicon, doped polysilicon, or single crystal silicon.