公开(公告)号：JP2003198274A

公开(公告)日：2003-07-11

申请号：JP2002234488

申请日：2002-08-12

Applicant: ST MICROELECTRONICS SRL

Inventor： ZUFFADA MAURIZIO ,  BETTI GIORGIO ,  CHRAPPAN SOLDAVINI FRANCESCO ,  HASSNER MARTIN AURELIANO

IPC: H03F1/34 ,  H03H11/48

Abstract: PROBLEM TO BE SOLVED: To easily integrate an electronic circuit having a nonlinear passive element. SOLUTION: The circuit refers to nonlinear electronic equipment, especially in a nonlinear capacitor, more specifically, to the electronic circuit device that can be integrated on a semiconductor substrate (not limited). A nonlinear device is advantageously set to be a capacitor consisting of the feedback loop of a plurality of active blocks (2, 5, and 6), that are mutually subjected to cascade connection. Further, the invention can be integrated with or can be used relating to a network including other pieces of nonlinear device. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003142988A

公开(公告)日：2003-05-16

申请号：JP2002234482

申请日：2002-08-12

Applicant: ST MICROELECTRONICS SRL

Inventor： ZUFFADA MAURIZIO ,  BETTI GIORGIO ,  CHRAPPAN SOLDAVINI FRANCESCO ,  HASSNER MARTIN AURELIANO

IPC: H01L21/822 ,  H01L27/04 ,  H03H11/48

Abstract: PROBLEM TO BE SOLVED: To easily integrate an electronic circuit having a non-linear passive element. SOLUTION: The invention relates to a non-linear electronic device and, more particularly, to a non-linear inductor. More specifically, but not exclusively, the invention relates to an electronic circuit device that may be integrated on a semiconductor substrate. Advantageously, the non-linear device is a inductor formed by a feedback loop of cascade connected active blocks (2, 5, 6). Moreover, the invention may be integrated or used in association with a circuit network including other non-linear devices.

公开(公告)号：DE60130884D1

公开(公告)日：2007-11-22

申请号：DE60130884

申请日：2001-08-10

Applicant: IBM ,  ST MICROELECTRONICS SRL

Inventor： ZUFFADA MAURIZIO ,  BETTI GIORGIO ,  CHRAPPAN SOLDAVINI FRANCESCO ,  HASSNER MARTIN AURELIANO

IPC: H03F1/34 ,  H03H11/48

Abstract: The invention relates to a non-linear electronic device and, more particularly, to a non-linear capacitor. More specifically, but not exclusively, the invention relates to an electronic circuit device that may be integrated on a semiconductor substrate. Advantageously, the non-linear device is a capacitor formed by a feedback loop of cascade connected active blocks (2, 5, 6). Moreover, the invention may be integrated or used in association with a circuit network including other non-linear devices.

公开(公告)号：ITMI20001950A1

公开(公告)日：2002-03-05

申请号：ITMI20001950

申请日：2000-09-05

Applicant: ST MICROELECTRONICS SRL

Inventor： CHRAPPAN SOLDAVINI FRANCESCO

IPC: H03K17/06 ,  H03K17/687

Abstract: A drive circuit for controlled edge power elements is described. In one embodiment the drive circuit for controlled edge power elements comprises: a first integrating circuit having a first input suitable for receiving in input a first drive signal; an integrating capacitor coupled to said integrating circuit; a first power element driven by said first integrating circuit and suitable for driving a load, said load having a first terminal. The said first integrating circuit includes a first current amplifier and said integrating capacitor is coupled between said first input and a predetermined reference voltage.

公开(公告)号：DE69813843D1

公开(公告)日：2003-05-28

申请号：DE69813843

申请日：1998-12-23

Applicant: ST MICROELECTRONICS SRL

Inventor： GALBIATI EZIO ,  PAPILLO LORENZO ,  CHRAPPAN SOLDAVINI FRANCESCO

IPC: G06F1/025 ,  H02M7/5387

Abstract: In driving a load in a PWM mode in function of numeric command values of a certain N number of bits by converting the current numeric command value in at least a driving PWM signal (PWM_A, PWM_B) having a fixed frequency and a duty cycle proportional to the numeric command value, comparing through a comparator (COMPARATOR) the N bit numeric value with the counter of an up/down counter of the same number (N) of bits (N BIT UP/DOWN COUNTER) functioning in a continuous mode at the frequency of a system's clock signal (SysClk), the definition of the conversion may be enhanced withtout correspondingly increasing the number of bits of the UP/DOWN COUNTER. This is achieved by incrementing by more than a unit (N+3) the number of bits on which a certain command value is mapped; converting the N most significant bits with the exception of said additional bits of said command value by means of said comparator and up/down counter; decoding said additional bits by generating a corresponding plurality of intermediate levels of variation of the duty cycle, each of which has a duration of half a clock period (SysClk/2) producing a plurality of signals, outphased among each other by half a clock period (A, B, C, D, B, A', B', C', D', E'); generating said driving PWM signal (IN_A, IN_B) by multiplating (MULTIPLEXER) said signals outphased among each other by half a clock period, carrying out logic combinations of such signals in function of the most significative bit (MSB) of the numeric command value and of said least significative additional bits.

公开(公告)号：DE69518973T2

公开(公告)日：2001-02-22

申请号：DE69518973

申请日：1995-05-19

Applicant: ST MICROELECTRONICS SRL

Inventor： CHRAPPAN SOLDAVINI FRANCESCO ,  SALINA ALBERTO

IPC: H01L21/60 ,  H01L21/66 ,  H01L21/822 ,  G01R31/02 ,  H01L23/482 ,  H01L23/528 ,  H01L27/04 ,  H01L21/00

Abstract: A device presenting split contact pad portions (31a, 31b, 32a, 32b, 33a, 33b, 34a, 34b), one for each multiple bonding wire (44a, 44b), and metal connecting strips, the end portion (37a, 37b, 38a, 38b, 39a, 39b, 40a, 40b) of which is also split into parallel strip segments, each connected to a respective contact pad, so as to form a plurality of parallel current paths between an externally connected node (22-25) and the contact pin (27-30). When current is supplied (59) along the connecting strip, therefore, this produces a voltage drop along each segment connected to a sound bonding wire, but not along the segments connected to broken or nonbonded wires; and by determining (50) the existence of a voltage difference between the contact pad portions, it is possible to detect the interruption of one or more of the bonding wires.

公开(公告)号：DE69518973D1

公开(公告)日：2000-11-02

申请号：DE69518973

申请日：1995-05-19

Applicant: ST MICROELECTRONICS SRL

Inventor： CHRAPPAN SOLDAVINI FRANCESCO ,  SALINA ALBERTO

IPC: H01L21/60 ,  H01L21/66 ,  H01L21/822 ,  G01R31/02 ,  H01L23/482 ,  H01L23/528 ,  H01L27/04 ,  H01L21/00

Abstract: A device presenting split contact pad portions (31a, 31b, 32a, 32b, 33a, 33b, 34a, 34b), one for each multiple bonding wire (44a, 44b), and metal connecting strips, the end portion (37a, 37b, 38a, 38b, 39a, 39b, 40a, 40b) of which is also split into parallel strip segments, each connected to a respective contact pad, so as to form a plurality of parallel current paths between an externally connected node (22-25) and the contact pin (27-30). When current is supplied (59) along the connecting strip, therefore, this produces a voltage drop along each segment connected to a sound bonding wire, but not along the segments connected to broken or nonbonded wires; and by determining (50) the existence of a voltage difference between the contact pad portions, it is possible to detect the interruption of one or more of the bonding wires.

公开(公告)号：ITMI20001951D0

公开(公告)日：2000-09-05

申请号：ITMI20001951

申请日：2000-09-05

Applicant: ST MICROELECTRONICS SRL

Inventor： CHRAPPAN SOLDAVINI FRANCESCO

IPC: H03F3/345 ,  H03F3/45

Abstract: A current amplifier includes an input branch having a first input; an output branch coupled to said input branch; a bias branch suitable for biasing said input branch. The input branch comprises at least one switch commanded by a first bias voltage supplied by said bias branch so as to substantially block the current flowing in said input branch and consequently substantially block the current flowing in said output branch when the current applied to said first input is null.

公开(公告)号：IT1318856B1

公开(公告)日：2003-09-10

申请号：ITMI20001999

申请日：2000-09-14

Applicant: ST MICROELECTRONICS SRL

Inventor： CHRAPPAN SOLDAVINI FRANCESCO ,  FONTANELLA LUCA

IPC: H02M1/08 ,  H02M3/158 ,  H02P6/18 ,  H03K5/1536

Abstract: The present invention relates a current zero crossing detecting circuit including a PWM driving half bridge circuit, which generates an output signal (OUT) and a signal synchronous with the high impedance condition of said PWM driving half bridge circuit. Said inventive circuit has the characteristic of comprising detecting means (DFLIP, COMP) synchronous with said signal synchronous with the high impedance condition of said PWM driving half bridge circuit and said output signal (OUT), and said detecting means generating a direction signal (DIR_COR) showing the current direction flowing in said pulse width modulation circuit.

公开(公告)号：IT1318818B1

公开(公告)日：2003-09-10

申请号：ITMI20001950

申请日：2000-09-05

Applicant: ST MICROELECTRONICS SRL

Inventor： CHRAPPAN SOLDAVINI FRANCESCO

IPC: H03K17/06 ,  H03K17/687

Abstract: A drive circuit for controlled edge power elements is described. In one embodiment the drive circuit for controlled edge power elements comprises: a first integrating circuit having a first input suitable for receiving in input a first drive signal; an integrating capacitor coupled to said integrating circuit; a first power element driven by said first integrating circuit and suitable for driving a load, said load having a first terminal. The said first integrating circuit includes a first current amplifier and said integrating capacitor is coupled between said first input and a predetermined reference voltage.