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    INTEGRATED ELECTRONIC CIRCUIT
    1.
    发明专利
    INTEGRATED ELECTRONIC CIRCUIT 审中-公开

    公开(公告)号：JP2003198274A

    公开(公告)日：2003-07-11

    申请号：JP2002234488

    申请日：2002-08-12

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZUFFADA MAURIZIO ,  BETTI GIORGIO ,  CHRAPPAN SOLDAVINI FRANCESCO ,  HASSNER MARTIN AURELIANO

    IPC: H03F1/34 ,  H03H11/48

    Abstract: PROBLEM TO BE SOLVED: To easily integrate an electronic circuit having a nonlinear passive element. SOLUTION: The circuit refers to nonlinear electronic equipment, especially in a nonlinear capacitor, more specifically, to the electronic circuit device that can be integrated on a semiconductor substrate (not limited). A nonlinear device is advantageously set to be a capacitor consisting of the feedback loop of a plurality of active blocks (2, 5, and 6), that are mutually subjected to cascade connection. Further, the invention can be integrated with or can be used relating to a network including other pieces of nonlinear device. COPYRIGHT: (C)2003,JPO

    INTEGRATED ELECTRONIC CIRCUIT
    2.
    发明专利
    INTEGRATED ELECTRONIC CIRCUIT 审中-公开

    公开(公告)号：JP2003142988A

    公开(公告)日：2003-05-16

    申请号：JP2002234482

    申请日：2002-08-12

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZUFFADA MAURIZIO ,  BETTI GIORGIO ,  CHRAPPAN SOLDAVINI FRANCESCO ,  HASSNER MARTIN AURELIANO

    IPC: H01L21/822 ,  H01L27/04 ,  H03H11/48

    Abstract: PROBLEM TO BE SOLVED: To easily integrate an electronic circuit having a non-linear passive element. SOLUTION: The invention relates to a non-linear electronic device and, more particularly, to a non-linear inductor. More specifically, but not exclusively, the invention relates to an electronic circuit device that may be integrated on a semiconductor substrate. Advantageously, the non-linear device is a inductor formed by a feedback loop of cascade connected active blocks (2, 5, 6). Moreover, the invention may be integrated or used in association with a circuit network including other non-linear devices.

    3.
    发明专利
    未知

    公开(公告)号：DE60130885D1

    公开(公告)日：2007-11-22

    申请号：DE60130885

    申请日：2001-08-10

    Applicant: IBM ,  ST MICROELECTRONICS SRL

    Inventor： ZUFFADA MAURIZIO ,  BETTI GIORGIO ,  CHRAPPAN SOLDAVINI F STMICROEL ,  HASSNER MARTIN AURELIANO

    IPC: H01L21/822 ,  H03H11/48 ,  H01L27/04

    Abstract: The invention relates to a non-linear electronic device and, more particularly, to a non-linear inductor. More specifically, but not exclusively, the invention relates to an electronic circuit device that may be integrated on a semiconductor substrate. Advantageously, the non-linear device is a inductor formed by a feedback loop of cascade connected active blocks (2, 5, 6). Moreover, the invention may be integrated or used in association with a circuit network including other non-linear devices.

    4.
    发明专利
    未知

    公开(公告)号：DE60130884D1

    公开(公告)日：2007-11-22

    申请号：DE60130884

    申请日：2001-08-10

    Applicant: IBM ,  ST MICROELECTRONICS SRL

    Inventor： ZUFFADA MAURIZIO ,  BETTI GIORGIO ,  CHRAPPAN SOLDAVINI FRANCESCO ,  HASSNER MARTIN AURELIANO

    IPC: H03F1/34 ,  H03H11/48

    Abstract: The invention relates to a non-linear electronic device and, more particularly, to a non-linear capacitor. More specifically, but not exclusively, the invention relates to an electronic circuit device that may be integrated on a semiconductor substrate. Advantageously, the non-linear device is a capacitor formed by a feedback loop of cascade connected active blocks (2, 5, 6). Moreover, the invention may be integrated or used in association with a circuit network including other non-linear devices.

    7.
    发明专利
    未知

    公开(公告)号：DE69424229T2

    公开(公告)日：2000-11-30

    申请号：DE69424229

    申请日：1994-06-27

    Applicant: IBM

    Inventor： HASSNER MARTIN AURELIANO ,  KARNIN EHUD DOV ,  SCHWIEGELSHOHN UWE ,  TAMURA TETSUYA

    IPC: G06F5/00 ,  G06T9/00 ,  H03M7/30 ,  H04B1/66 ,  G06F7/02

    Abstract: An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer 22 comprises an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array. The parameters i and j are selected to limit the number of comparators required to achieve a desired degree of efficiency in executing the algorithm based upon a trade-off of algorithm execution speed versus hardware cost. A priority encoder calculates from signals output by the slice units each j,i address in which a matching sequence is identified, but it outputs the address of only one (such as the smallest) of these addresses.

    8.
    发明专利
    未知

    公开(公告)号：DE69614772T2

    公开(公告)日：2002-07-04

    申请号：DE69614772

    申请日：1996-06-10

    Applicant: IBM

    Inventor： HASSNER MARTIN AURELIANO ,  TAMURA TETSUYA ,  WINOGRAD SHMUEL

    IPC: G11B20/10 ,  G11B20/14 ,  G11B20/18

    Abstract: Parallel ML processing of an analog signal in a RLL-coded channel in which (1) vectors for a current state of the channel and the next state of the channel are computed using Walsh transform vector coefficients of the analog signal; (2) current state vectors and next state vectors and values of vectors precomputed in analog matched filters are used to generate vector scalar products which are compared against preselected threshold values for generating binary decision outputs that are used in digital sequential finite state machines to generate ML symbol decisions; and (3) ML symbol decisions are fed back and used to subtract the intersymbol interference value of the current state vector from the vector of the next state to transform the next state vector into an updated current state vector.

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