公开(公告)号：US20130187669A1

公开(公告)日：2013-07-25

申请号：US13746149

申请日：2013-01-21

Applicant: IMEC

Inventor： Murali Jayapala ,  Geert Van Der Plas ,  Veronique Rochus ,  Xavier Rottenberg ,  Simone Severi ,  Stéphane Donnay

IPC: G02B27/00

CPC classification number: G02B27/00 ,  G02B1/00 ,  G02B6/352 ,  G02B6/359 ,  G02B26/0825 ,  G02B26/0841 ,  G02B2207/00 ,  H04N1/00

Abstract: A built-in self-calibration system and method for a micro-mirror array device, for example, operating as a variable focal length lens is described. The calibration method comprises determining a capacitance value for each micro-mirror element in the array device at a number of predetermined reference angles to provide a capacitance-reference angle relationship. From the capacitance values, an interpolation step is carried to determine intermediate tilt angles for each micro-mirror element in the array. A voltage sweep is applied to the micro-mirror array and capacitance values, for each micro-mirror element in the array, are measured. For a capacitance value that matches one of the values in the capacitance-reference angle relationship, the corresponding voltage is linked to the associated tilt angle to provide a voltage-tilt angle characteristic which then stored in a memory for subsequent use.

Abstract translation: 描述了用作微反射镜阵列器件的内置自校准系统和方法，例如作为可变焦距透镜操作。 校准方法包括以多个预定参考角度确定阵列器件中的每个微镜元件的电容值，以提供电容参考角度关系。 根据电容值，进行插值步骤以确定阵列中的每个微镜元件的中间倾斜角度。 对微镜阵列施加电压扫描，并测量阵列中每个微镜元件的电容值。 对于与电容参考角度关系中的一个值匹配的电容值，相应的电压与相关联的倾斜角度相关联，以提供电压倾斜角特性，然后将其存储在存储器中用于随后的使用。

公开(公告)号：US11257764B2

公开(公告)日：2022-02-22

申请号：US16874446

申请日：2020-05-14

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Geert Van Der Plas

IPC: H01L23/538 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/50 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit (IC) chip that includes a semiconductor substrate including active devices on its front side, and at least part of a power delivery network (PDN) on its back side, is disclosed. In one aspect, the PDN includes a power supply terminal (Vdd) and a reference terminal (Vss) at the back of the IC. A plurality of TSV (Through Semiconductor Via) connections through the substrate bring the power to the front of the substrate. A field effect transistor is integrated at the back side of the substrate, and includes a source electrode, a drain electrode, and a gate electrode, which are contacted at the back side of the substrate. The IC further includes a gate control terminal for controlling the gate voltage. The transistor is coupled between the power supply terminal and one or more of the active devices of the IC.

公开(公告)号：US09201241B2

公开(公告)日：2015-12-01

申请号：US13746149

申请日：2013-01-21

Applicant: IMEC

Inventor： Murali Jayapala ,  Geert Van Der Plas ,  Veronique Rochus ,  Xavier Rottenberg ,  Simone Severi ,  Stéphane Donnay

IPC: G01R27/26 ,  G02B27/00 ,  G02B1/00 ,  H04N1/00 ,  G02B6/35 ,  G02B26/08

CPC classification number: G02B27/00 ,  G02B1/00 ,  G02B6/352 ,  G02B6/359 ,  G02B26/0825 ,  G02B26/0841 ,  G02B2207/00 ,  H04N1/00

Abstract: A built-in self-calibration system and method for a micro-mirror array device, for example, operating as a variable focal length lens is described. The calibration method comprises determining a capacitance value for each micro-mirror element in the array device at a number of predetermined reference angles to provide a capacitance-reference angle relationship. From the capacitance values, an interpolation step is carried to determine intermediate tilt angles for each micro-mirror element in the array. A voltage sweep is applied to the micro-mirror array and capacitance values, for each micro-mirror element in the array, are measured. For a capacitance value that matches one of the values in the capacitance-reference angle relationship, the corresponding voltage is linked to the associated tilt angle to provide a voltage-tilt angle characteristic which then stored in a memory for subsequent use.

Abstract translation: 描述了用作微反射镜阵列器件的内置自校准系统和方法，例如作为可变焦距透镜操作。 校准方法包括以多个预定参考角度确定阵列器件中的每个微镜元件的电容值，以提供电容参考角度关系。 根据电容值，进行插值步骤以确定阵列中的每个微镜元件的中间倾斜角度。 对微镜阵列施加电压扫描，并测量阵列中每个微镜元件的电容值。 对于与电容参考角度关系中的一个值匹配的电容值，相应的电压与相关联的倾斜角度相关联，以提供电压倾斜角特性，然后将其存储在存储器中用于随后的使用。

公开(公告)号：US12154830B2

公开(公告)日：2024-11-26

申请号：US17580020

申请日：2022-01-20

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Anshul Gupta ,  Geert Van Der Plas

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method of producing a gate cut in a semiconductor component is provided. In one aspect, an array of nano-sized semiconductor fins is processed on a semiconductor substrate. Rails may be buried in the substrate and in a layer of dielectric material that isolates neighboring fins from each other. The rails may extend in the direction of the fins and each rail may be situated between two adjacent fins. The rails may be buried power rails for enabling the formation of a power delivery network at the back of an integrated circuit chip. At the front side of the substrate, one or more gate structures are produced. The gate structures extend transversally, or perpendicularly, with respect to the fins and the rails. A gate cut is produced by forming an opening from the back side of the substrate, and removing a portion of the gate structure at the bottom of the opening, thereby creating a gate cut that is aligned to the sidewalls of the rail. In another aspect, a semiconductor component, such as an integrated circuit, includes a gate cut that is aligned to the sidewalls of a buried contact rail.

公开(公告)号：US20200373242A1

公开(公告)日：2020-11-26

申请号：US16874446

申请日：2020-05-14

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Geert Van Der Plas

IPC: H01L23/538 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/50 ,  H01L21/768

Abstract: An integrated circuit (IC) chip that includes a semiconductor substrate including active devices on its front side, and at least part of a power delivery network (PDN) on its back side, is disclosed. In one aspect, the PDN includes a power supply terminal (Vdd) and a reference terminal (Vss) at the back of the IC. A plurality of TSV (Through Semiconductor Via) connections through the substrate bring the power to the front of the substrate. A field effect transistor is integrated at the back side of the substrate, and includes a source electrode, a drain electrode, and a gate electrode, which are contacted at the back side of the substrate. The IC further includes a gate control terminal for controlling the gate voltage. The transistor is coupled between the power supply terminal and one or more of the active devices of the IC.