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公开(公告)号：US12188895B2
公开(公告)日：2025-01-07
申请号：US17692717
申请日：2022-03-11
Applicant: IMEC VZW
Inventor： David Barge , Bert Du Bois , Simone Severi , Ashesh Ray Chaudhuri
IPC: H01L21/00 , G01N27/414
Abstract: A method for forming a nanopore transistor and a nanopore transistor is provided. The method includes: (a) forming an aperture in a filler material by: (i) providing a fin comprising a semiconductor layer and a top layer; (ii) patterning the top layer to form a pillar; (iii) embedding the pillar in a filler material; (iv) removing the pillar, leaving an aperture; (v) lining the aperture with a spacer material; (b) forming a nanopore by etching through the aperture; (b) lining the nanopore with a dielectric, (c) forming a source and a drain by either: between steps a.ii and a.iii, doping the bottom semiconductor layer by using the pillar as a mask, or after step c, filling the aperture with a sealing material, thereby forming a post; removing the filler material; doping the bottom semiconductor layer by using the post as a mask; and removing the sealing material.
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公开(公告)号：US11676851B2
公开(公告)日：2023-06-13
申请号：US16957090
申请日：2018-12-19
Applicant: IMEC VZW
Inventor： Aurelie Humbert , Simone Severi
IPC: H01L21/762 , G01N27/414
CPC classification number: H01L21/76251 , G01N27/4145 , G01N27/4146 , G01N27/4148
Abstract: According to an aspect of the present inventive concept there is provided a method for manufacturing a fluid sensor device comprising: bonding a silicon-on-insulator arrangement comprising a silicon wafer, a buried oxide, a silicon layer, and a first dielectric layer, to a CMOS arrangement comprising a metallization layer and a planarized dielectric layer, wherein the bonding is performed via the first dielectric layer and the planarized dielectric layer; forming a fin-FET arrangement in the silicon layer, wherein the fin-FET arrangement is configured to function as a fluid sensitive fin-FET arrangement; removing the buried oxide and the silicon wafer; forming a contact to the metallization layer and the fin-FET arrangement, wherein the contact comprises an interconnecting structure configured to interconnect the metallization layer and the fin-FET arrangement; forming a channel comprising an inlet and an outlet, wherein the channel is configured to allow a fluid comprising an analyte to contact the fin-FET arrangement.
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公开(公告)号：US10267733B2
公开(公告)日：2019-04-23
申请号：US15312116
申请日：2015-05-22
Applicant: IMEC VZW
Inventor： Pol Van Dorpe , Liesbet Lagae , Peter Peumans , Andim Stassen , Philippe Helin , Bert Du Bois , Simone Severi
Abstract: The present disclosure relates to semiconductor devices for detecting fluorescent particles. At least one embodiment relates to an integrated semiconductor device for detecting fluorescent tags. The device includes a first layer, a second layer, a third layer, a fourth layer, and a fifth layer. The first layer includes a detector element. The second layer includes a rejection filter. The third layer is fabricated from dielectric material. The fourth layer is an optical waveguide configured and positioned such that a top surface of the fourth layer is illuminated with an evanescent tail of excitation light guided by the optical waveguide when the fluorescent tags are present. The fifth layer includes a microfluidic channel. The optical waveguide is configured and positioned such that the microfluidic channel is illuminated with the evanescent tail. The detector element is positioned such that light from activated fluorescent tags can be received.
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公开(公告)号：US20170082544A1
公开(公告)日：2017-03-23
申请号：US15312116
申请日：2015-05-22
Applicant: IMEC VZW
Inventor： Pol Van Dorpe , Liesbet Lagae , Peter Peumans , Andim Stassen , Philippe Helin , Bert Du Bois , Simone Severi
IPC: G01N21/64
CPC classification number: G01N21/6428 , G01N21/6454 , G01N21/648 , G01N21/7703 , G01N2201/0873
Abstract: The present disclosure relates to semiconductor devices for detecting fluorescent particles. At least one embodiment relates to an integrated semiconductor device for detecting fluorescent tags. The device includes a first layer, a second layer, a third layer, a fourth layer, and a fifth layer. The first layer includes a detector element. The second layer includes a rejection filter. The third layer is fabricated from dielectric material. The fourth layer is an optical waveguide configured and positioned such that a top surface of the fourth layer is illuminated with an evanescent tail of excitation light guided by the optical waveguide when the fluorescent tags are present. The fifth layer includes a microfluidic channel. The optical waveguide is configured and positioned such that the microfluidic channel is illuminated with the evanescent tail. The detector element is positioned such that light from activated fluorescent tags can be received.
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公开(公告)号：US20220334079A1
公开(公告)日：2022-10-20
申请号：US17692717
申请日：2022-03-11
Applicant: IMEC VZW
Inventor： David Barge , Bert Du Bois , Simone Severi , Ashesh Ray Chaudhuri
IPC: G01N27/414
Abstract: A method for forming a nanopore transistor and a nanopore transistor is provided. The method includes: (a) forming an aperture in a filler material by: (i) providing a fin comprising a semiconductor layer and a top layer; (ii) pattering the top layer to form a pillar; (iii) embedding the pillar in a filler material; (iv) removing the pillar, leaving an aperture; (v) lining the aperture with a spacer material; (b) forming a nanopore by etching through the aperture; (b) lining the nanopore with a dielectric, (c) forming a source and a drain by either: between steps a.ii and a.iii, doping the bottom semiconductor layer by using the pillar as a mask, or after step c, filling the aperture with a sealing material, thereby forming a post; removing the filler material; doping the bottom semiconductor layer by using the post as a mask; and removing the sealing material.
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Patent Agency Ranking
公开(公告)号：US11372158B2
公开(公告)日：2022-06-28
申请号：US16703242
申请日：2019-12-04
Applicant: IMEC VZW , KATHOLIEKE UNIVERSITEIT LEUVEN
Inventor： Wouter Jan Westerveld , Veronique Rochus , Simone Severi , Roelof Jansen
Abstract: A waveguide for guiding an electro-magnetic wave comprises: a first waveguide part; and a second waveguide part; wherein the first waveguide part has a first width in a first direction (Y) perpendicular to the direction of propagation of the electro-magnetic wave and the second waveguide part has a second width in the first direction (Y), wherein the second width is larger than the first width; and wherein the first and the second waveguide parts are spaced apart by a gap in a second direction (Z) perpendicular to the first and second planes in which the waveguide parts are formed, wherein the gap has a size which is sufficiently small such that the first and second waveguide parts unitely form a single waveguide for guiding the electro-magnetic wave. The waveguide may be used in numerous applications, such as in a photonic integrated circuit, in a sensor or in an actuator.
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公开(公告)号：US20130187669A1
公开(公告)日：2013-07-25
申请号：US13746149
申请日：2013-01-21
Applicant: IMEC
Inventor： Murali Jayapala , Geert Van Der Plas , Veronique Rochus , Xavier Rottenberg , Simone Severi , Stéphane Donnay
IPC: G02B27/00
CPC classification number: G02B27/00 , G02B1/00 , G02B6/352 , G02B6/359 , G02B26/0825 , G02B26/0841 , G02B2207/00 , H04N1/00
Abstract: A built-in self-calibration system and method for a micro-mirror array device, for example, operating as a variable focal length lens is described. The calibration method comprises determining a capacitance value for each micro-mirror element in the array device at a number of predetermined reference angles to provide a capacitance-reference angle relationship. From the capacitance values, an interpolation step is carried to determine intermediate tilt angles for each micro-mirror element in the array. A voltage sweep is applied to the micro-mirror array and capacitance values, for each micro-mirror element in the array, are measured. For a capacitance value that matches one of the values in the capacitance-reference angle relationship, the corresponding voltage is linked to the associated tilt angle to provide a voltage-tilt angle characteristic which then stored in a memory for subsequent use.
Abstract translation: 描述了用作微反射镜阵列器件的内置自校准系统和方法，例如作为可变焦距透镜操作。 校准方法包括以多个预定参考角度确定阵列器件中的每个微镜元件的电容值，以提供电容参考角度关系。 根据电容值，进行插值步骤以确定阵列中的每个微镜元件的中间倾斜角度。 对微镜阵列施加电压扫描，并测量阵列中每个微镜元件的电容值。 对于与电容参考角度关系中的一个值匹配的电容值，相应的电压与相关联的倾斜角度相关联，以提供电压倾斜角特性，然后将其存储在存储器中用于随后的使用。
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公开(公告)号：US20210300752A1
公开(公告)日：2021-09-30
申请号：US17203026
申请日：2021-03-16
Applicant: IMEC VZW
Inventor： Giuseppe Fiorentino , Aurelie Humbert , Simone Severi , Benjamin Jones
IPC: B81C1/00
Abstract: A method for fabricating a microfluidic device includes providing an assembly that includes a first silicon substrate having a hydrophilic silicon oxide top surface that includes a microfluidic channel and a second silicon substrate having a hydrophilic silicon oxide bottom surface directly bonded on the top surface of the first silicon substrate, the second silicon substrate including fluidic access holes giving fluidic access to the microfluidic channel. The method also includes exposing the assembly to oxidative species including one or more oxygen atoms and to heat so as to form silicon oxide at a surface of the access holes and of the microfluidic channel.
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公开(公告)号：US09217861B2
公开(公告)日：2015-12-22
申请号：US14373071
申请日：2013-01-18
Applicant: IMEC VZW
Inventor： Murali Jayapala , Geert Van der Plas , Veronique Rochus , Xavier Rottenberg , Simone Severi
CPC classification number: G02B26/0833 , G02B5/08 , G02B7/182 , G02B17/0896 , G02B26/08 , G02B26/0825 , G02B26/0841 , G02B27/10 , H04N13/322 , H04N13/365
Abstract: Micro-mirror arrays configured for use in a variable focal length lens are described herein. An example variable focal length lens comprises a micro-mirror array having a plurality of micro-mirror elements arranged in at least a first section and a second section. Each micro-mirror element has a tilt axis and comprises, on each of two opposing sides of the tilt axis, (i) at least one actuation electrode, (ii) at least one measurement electrode, and (iii) at least one stopper. Additionally, each micro-mirror element in the first section has a first tilt angle range, and each micro-mirror element in the second section has a second tilt angle range, with the first tilt angle range being less than the second tilt angle range.
Abstract translation: 这里描述了配置用于可变焦距透镜的微镜阵列。 示例性可变焦距透镜包括具有布置在至少第一部分和第二部分中的多个微反射镜元件的微反射镜阵列。 每个微镜元件具有倾斜轴线，并且在倾斜轴线的两个相对侧的每一侧上包括（i）至少一个致动电极，（ii）至少一个测量电极，和（iii）至少一个止动器。 此外，第一部分中的每个微镜元件具有第一倾斜角范围，并且第二部分中的每个微镜元件具有第二倾斜角范围，其中第一倾斜角度范围小于第二倾斜角范围。
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公开(公告)号：US09201241B2
公开(公告)日：2015-12-01
申请号：US13746149
申请日：2013-01-21
Applicant: IMEC
Inventor： Murali Jayapala , Geert Van Der Plas , Veronique Rochus , Xavier Rottenberg , Simone Severi , Stéphane Donnay
CPC classification number: G02B27/00 , G02B1/00 , G02B6/352 , G02B6/359 , G02B26/0825 , G02B26/0841 , G02B2207/00 , H04N1/00
Abstract: A built-in self-calibration system and method for a micro-mirror array device, for example, operating as a variable focal length lens is described. The calibration method comprises determining a capacitance value for each micro-mirror element in the array device at a number of predetermined reference angles to provide a capacitance-reference angle relationship. From the capacitance values, an interpolation step is carried to determine intermediate tilt angles for each micro-mirror element in the array. A voltage sweep is applied to the micro-mirror array and capacitance values, for each micro-mirror element in the array, are measured. For a capacitance value that matches one of the values in the capacitance-reference angle relationship, the corresponding voltage is linked to the associated tilt angle to provide a voltage-tilt angle characteristic which then stored in a memory for subsequent use.
Abstract translation: 描述了用作微反射镜阵列器件的内置自校准系统和方法，例如作为可变焦距透镜操作。 校准方法包括以多个预定参考角度确定阵列器件中的每个微镜元件的电容值，以提供电容参考角度关系。 根据电容值，进行插值步骤以确定阵列中的每个微镜元件的中间倾斜角度。 对微镜阵列施加电压扫描，并测量阵列中每个微镜元件的电容值。 对于与电容参考角度关系中的一个值匹配的电容值，相应的电压与相关联的倾斜角度相关联，以提供电压倾斜角特性，然后将其存储在存储器中用于随后的使用。
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