Abstract:
PROBLEM TO BE SOLVED: To obtain polishing liquid for a chemical-mechanical polishing treatment process, which can be used for planarizing or patterning of a metal or a metal oxide. SOLUTION: In this polishing liquid, at least one kind of additive selected from among (a) water or water/alcohol mixture, (b) polycrystalline diamond powder, and (c) oxidizing agent, a complex forming agent, a surfactant and a group of organic base is contained. The removal rate can be improved, when planarizing or patterning the metal or the metal oxide by using the polishing liquid.
Abstract:
The present invention provides a sidewall oxygen diffusion barrier and method for fabricating the sidewall oxygen diffusion barrier to reduce the diffusion of oxygen to contact plugs during CW hole reactive ion etch processing of a ferroelectric capacitor of an FeRAM device. In one embodiment the sidewall barrier is formed from a substrate fence, while in another embodiment the sidewall barrier is formed by etching back an oxygen barrier.
Abstract:
A capacitor with improved reliability is disclosed. The capacitor includes a bottom electrode, a top electrode, and an intermediate layer therebetween. A contact, which is electrically coupled to the top electrode, is provided. At least a portion of the contact is offset from the capacitor. By offsetting the contact from the top electrode, the etch damage to the top electrode is reduced, thereby reducing or eliminating the need for the anneal to repair the etch damage.
Abstract:
The invention relates to a method for the production of a capacitor electrode (11) with a barrier structure (14.1) arranged beneath it. Said method comprises producing the barrier structure (14.1) by means of introducing a barrier support layer (16) and applying a CMP (chemical mechanical polishing) process.
Abstract:
The aim of the invention is to create a microelectronic structure which prevents oxidation of oxygen-sensitive structures (25). To this end, the microelectronic structure is provided with a conductive layer (10) consisting of a platinum iridium alloy. The iridium should hamper the oxygen diffusion through the conductive layer (10) by binding the oxygen when the microelectronic structure is treated in a oxygen-containing atmosphere. Oxidation-sensitive structures (25) are thus protected underneath the conductive layer (10).
Abstract:
In a capacitor and a method for its manufacture, a first electrode layer and a second electrode layer are formed such that a ferroelectric layer is situated between the first and second electrode layer. A first bilayer or multi-layer seed structure is formed between the ferroelectric layer and either the first electrode layer or the second electrode layer.
Abstract:
Production of a structured metal-containing layer on a semiconductor wafer comprises preparing a wafer with a substrate (1); arranging the metal-containing layer (4) on the substrate; arranging a mask layer (5) on the metal-containing layer; structuring the mask layer and the metal-containing layer; depositing a protective layer (6) on the mask layer and on the substrate; and chemical-mechanical polishing the protective layer and the mask layer, in which the protective layer and the mask layer are removed by an electrode and the electrode is exposed. Preferred Features: A barrier layer is applied to the substrate before applying the electrode. The barrier layer contains titanium or titanium nitride, tantalum or tantalum nitride or tantalum silicon nitride, or iridium or iridium oxide. The electrode contains platinum. The protective layer is made from silicon nitride. The mask layer contains silicon oxide.
Abstract:
Capacitor has a silicon-containing oxide layer, a barrier layer and an electrode layer on a substrate. Production of a capacitor comprises: (1) preparing a substrate (5) having a silicon-containing oxide layer (12), a barrier layer (35) and an electrode layer (30); (2) selectively etching the electrode layer and the barrier layer in one common or in subsequent steps to form an electrode (57) of the capacitor, where the oxide layer (12) below the barrier layer (35) is attacked by at least one etching step to a required degree; and (3) CVD depositing a metal in a oxidizing atmosphere and at a deposition temperature to form a polycrystalline metal oxide layer. An amorphous passivating edge (50) is produced on CVD deposition of the barrier layer.
Abstract:
The invention relates to a method for the production of a capacitor electrode (11) with a barrier structure (14.1) arranged beneath it. Said method comprises producing the barrier structure (14.1) by means of introducing a barrier support layer (16) and applying a CMP (chemical mechanical polishing) process.