SEMICONDUCTOR MEMORY CELLS
    3.
    发明申请

    公开(公告)号:WO2004027841A3

    公开(公告)日:2004-08-12

    申请号:PCT/EP0310117

    申请日:2003-09-11

    CPC classification number: H01L27/11502 H01L21/76895 H01L27/11507 H01L28/60

    Abstract: A capacitor with improved reliability is disclosed. The capacitor includes a bottom electrode, a top electrode, and an intermediate layer therebetween. A contact, which is electrically coupled to the top electrode, is provided. At least a portion of the contact is offset from the capacitor. By offsetting the contact from the top electrode, the etch damage to the top electrode is reduced, thereby reducing or eliminating the need for the anneal to repair the etch damage.

    Abstract translation: 公开了具有可靠性提高的电容器。 电容器包括底部电极,顶部电极和它们之间的中间层。 提供了电耦合到顶部电极的触点。 触点的至少一部分偏离电容器。 通过抵消与顶部电极的接触,对顶部电极的蚀刻损伤减小,从而减少或消除了退火以修复蚀刻损伤的需要。

    CAPACITOR ELECTRODE
    5.
    发明申请
    CAPACITOR ELECTRODE 审中-公开
    电容电极

    公开(公告)号:WO0036636A3

    公开(公告)日:2000-08-10

    申请号:PCT/DE9903926

    申请日:1999-12-08

    CPC classification number: H01L28/75 H01L28/55 H01L28/60

    Abstract: The aim of the invention is to create a microelectronic structure which prevents oxidation of oxygen-sensitive structures (25). To this end, the microelectronic structure is provided with a conductive layer (10) consisting of a platinum iridium alloy. The iridium should hamper the oxygen diffusion through the conductive layer (10) by binding the oxygen when the microelectronic structure is treated in a oxygen-containing atmosphere. Oxidation-sensitive structures (25) are thus protected underneath the conductive layer (10).

    Abstract translation: 它是要创建的微电子结构,其防止对氧敏感的结构(25)的氧化。 为了这个目的,在微电子结构的导电层(10)由铂铱合金制成。 铱应通过结合氧气阻碍通过导电层(10)中的氧扩散,从而保护用一种处理微电子结构的导电层(10)下方的氧化敏感的结构(25)在含氧气氛。

    8.
    发明专利
    未知

    公开(公告)号:DE19849542C2

    公开(公告)日:2002-07-11

    申请号:DE19849542

    申请日:1998-10-27

    Abstract: Capacitor has a silicon-containing oxide layer, a barrier layer and an electrode layer on a substrate. Production of a capacitor comprises: (1) preparing a substrate (5) having a silicon-containing oxide layer (12), a barrier layer (35) and an electrode layer (30); (2) selectively etching the electrode layer and the barrier layer in one common or in subsequent steps to form an electrode (57) of the capacitor, where the oxide layer (12) below the barrier layer (35) is attacked by at least one etching step to a required degree; and (3) CVD depositing a metal in a oxidizing atmosphere and at a deposition temperature to form a polycrystalline metal oxide layer. An amorphous passivating edge (50) is produced on CVD deposition of the barrier layer.

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