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    MASTER LATCH CIRCUIT WITH SIGNAL LEVEL DISPLACEMENT FOR A DYNAMIC FLIP-FLOP
    1.
    发明申请
    MASTER LATCH CIRCUIT WITH SIGNAL LEVEL DISPLACEMENT FOR A DYNAMIC FLIP-FLOP 审中-公开
    使用信号电平切换进行动态触发器的主锁存器切换

    公开(公告)号：WO2005039050A2

    公开(公告)日：2005-04-28

    申请号：PCT/EP2004009853

    申请日：2004-09-03

    Applicant: INFINEON TECHNOLOGIES AG ,  BERTHOLD JOERG ,  GEORGAKOS GEORG ,  HENZLER STEPHAN ,  SCHMITT-LANDSIEDEL DORIS

    Inventor： BERTHOLD JOERG ,  GEORGAKOS GEORG ,  HENZLER STEPHAN ,  SCHMITT-LANDSIEDEL DORIS

    IPC: H03K3/037 ,  H03K3/356

    CPC classification number: H03K3/037 ,  H03K3/356121

    Abstract: A master latch circuit (10) with signal level displacement for a flip-flop (1) clocked by a clock pulse signal (Clk), wherein the master latch circuit (10) comprises a signal delay circuit (13) which delays and inverts the clock pulse signal (ClK), resulting in a specific time delay (AT), and a circuit node (14) which, in a charging phase wherein the clock pulse signal (Clk) is logically low, is charged to an operational voltage (VB) and which, in an evaluation phase when the clock pulse signal (Clk) and delayed, inverted clock pulse signal (ClkDELAY) are logically high, is discharged according to a specific data signal (D), wherein the data signal controls only transistors of a single type (either only N-channel or only P-channel). The master latch circuit (10) has only one supply voltage .

    Abstract translation: MasterLatchschaltung（10）具有用于一个触发器信号电平移位（1）由一个时钟信号（CLK）的时钟频率，所述MasterLatchschaltung（10），包括：信号延迟电路（13），其具有所施加的时钟信号（CLK） 一定的时间延迟（AT）延迟和倒置; 和一个电路节点（14），其在充电阶段，其中所施加的时钟信号（CLK）为逻辑低电平时，到工作电压（VB）充电，并且当所施加的时钟信号（CLK）和延迟反相在评估阶段， 时钟信号（ClkDELAY）是逻辑高时，根据所施加的数据信号（d）的可放电，其中，所述数据信号驱动仅单一类型的晶体管（N-或P-沟道只）。 主锁存电路（10）仅具有单个电源电压。

    METHOD FOR DETERMINING THE CRITICAL PATH OF AN INTEGRATED CIRCUIT
    4.
    发明申请
    METHOD FOR DETERMINING THE CRITICAL PATH OF AN INTEGRATED CIRCUIT 审中-公开
    程序来确定关键路径上的集成电路

    公开(公告)号：WO02056208A3

    公开(公告)日：2004-01-08

    申请号：PCT/DE0104957

    申请日：2001-12-28

    Applicant: INFINEON TECHNOLOGIES AG ,  BERTHOLD JOERG ,  LORCH HENNING ,  EISELE MARTIN

    Inventor： BERTHOLD JOERG ,  LORCH HENNING ,  EISELE MARTIN

    IPC: G06F17/50

    CPC classification number: G06F17/5031

    Abstract: in order to determine the critical path of a circuit, firstly the paths, the mean path runtimes and the path runtime variations thereof are determined. Paths with similar statistical parameters are collated into path groups. A statistical group figure for each path group and a statistical total figure for all paths considered are than calculated. Finally the critical path is determined by means of a comparison of the group figures at or above a critical path runtime Tc taking into account the total figure.

    Abstract translation: 为的电路路径，它们的平均路径运送时间和其路径传播时间波动关键路径的确定首先确定。 具有类似的统计参数路径被合并成一个路径合奏。 然后被添加到每个路径合奏系综质谱和用于所有被计算的总统计测量所考虑的路径。 最后，将合奏质量要确定的电路的关键路径，考虑到总质量的在等于或高于比较的基础上的关键路径中转时间Tc。

    5.
    发明专利
    未知

    公开(公告)号：DE102008039560A1

    公开(公告)日：2009-04-16

    申请号：DE102008039560

    申请日：2008-08-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BERTHOLD JOERG ,  KAMP WINFRIED ,  ROTHACHER FRITZ

    IPC: H01L21/336

    Abstract: A method of fabricating an integrated circuit including arranging a plurality of cells to form a desired floor plan of the integrated circuit, wherein each cell comprises at least one transistor, forming a plurality of circuit constituents from the plurality of cells of the floor plan, wherein each circuit constituent comprises at least one cell and belongs to one of a plurality circuit constituent types, and applying mechanical stress to channel regions of the at least one transistor of each cell based on the circuit constituent type of the circuit constituent to which the cell belongs.

    9.
    发明专利
    未知

    公开(公告)号：DE102004036956B3

    公开(公告)日：2006-03-23

    申请号：DE102004036956

    申请日：2004-07-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HENZLER STEPHAN ,  BERTHOLD JOERG ,  GEORGAKOS GEORG ,  SCHMITT-LANDSIEDEL DORIS

    IPC: H03K19/00 ,  H03K19/094

    Abstract: Logic activation circuit for switching a logic circuit having at least one supply voltage line on or off, said logic activation circuit having: (a) at least one voltage supply switching device for connecting a supply voltage to a supply voltage line of the logic circuit in a manner dependent on a changeover control signal that is applied to a control terminal of the voltage supply switching device; and having (b) a charge equalization switching device which, in a manner dependent on a control switching pulse, connects the supply voltage line of the logic circuit to the control terminal of the voltage supply switching device for the duration of the control switching pulse so that charge equalization is effected between the supply voltage line and the control terminal of the voltage supply switching device in order to generate the changeover control signal.

    Circuit for read-out memory cells of memory matrix
    10.
    发明专利
    Circuit for read-out memory cells of memory matrix 未知

    公开(公告)号：DE10121199A1

    公开(公告)日：2002-11-07

    申请号：DE10121199

    申请日：2001-04-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BERTHOLD JOERG

    IPC: G11C8/08 ,  G11C11/418 ,  G11C11/4074

    Abstract: The circuit comprises an address decoder (3) for contacting individual cells (2) via word (WL) and bit lines (BL), which has a word line driver (5) for each word line. The driver is coupled to first supply potential (VDD1) for wordline activation according to an output signal of the decoder. There is an output terminal for output signal, corresp. to memory cell content.The word line drivers are coupled to second supply potential (VDD2), higher than the first one. On connection to the higher potential, the drivers activate the respective word line, corresp. to decoder output signal, onto a second voltage level higher than the first one. Independent claims are included for read-out method from memory cells.

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