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    Differential current evaluation circuit for evaluating memory state of sram semiconductor memory cell, and sense amplifier circuit
    1.
    发明专利
    Differential current evaluation circuit for evaluating memory state of sram semiconductor memory cell, and sense amplifier circuit 审中-公开
    用于评估SRAM半导体存储器单元和感测放大器电路的存储状态的差分电流评估电路

    公开(公告)号：JP2003323800A

    公开(公告)日：2003-11-14

    申请号：JP2003127195

    申请日：2003-05-02

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： WICHT BERNHARD ,  SCHMITT-LANDSIEDEL DORIS ,  LARGUIER YEAN-YVES

    IPC: G11C7/06 ,  G11C11/413 ,  G11C11/419 ,  G11C29/12 ,  G11C29/00

    CPC classification number: G11C11/419 ,  G11C7/062 ,  G11C2207/063

    Abstract: PROBLEM TO BE SOLVED: To improve circuit structure for reading and evaluating the memory state in a semiconductor memory cell.
    SOLUTION: A differential current evaluation circuit (SBS) is provided with input section resistance adjusting means (MIN, MINB) of a differential amplifier (DV) and a current evaluation circuit (SBS). These means (MIN, MINB) are connected to the output parts (outp, outn) and the input parts (inn, inp) of the differential amplifier (DV) and signal lines (BL, BLB), which are electrically connected also to the input parts (inn, inp) of the differential amplifier (DV). A sense amplifier circuit (LV) is provided with a circuit part (ST2). The differential current evaluation circuit (SBS) and the sense amplifier circuit (LV) are arranged in circuit structure for reading and evaluating the memory state of a semiconductor memory cell. A current evaluation circuit is activated, before a reading process and automatically inactivated, immediately after finishing the reading process by a circuit (STAD) for automatic inactivation.
    COPYRIGHT: (C)2004,JPO

    Abstract translation: 要解决的问题：提高用于读取和评估半导体存储单元中的存储器状态的电路结构。 解决方案：差分电流评估电路（SBS）具有差分放大器（DV）和电流评估电路（SBS）的输入部分电阻调节装置（MIN，MINB）。 这些装置（MIN，MINB）连接到差分放大器（DV）和信号线（BL，BLB）的输出部分（outp，outn）和输入部分（inn，inp），它们也电连接到 差分放大器（DV）的输入部分（inn，inp）。 读出放大器电路（LV）具有电路部分（ST2）。 差分电流评估电路（SBS）和读出放大器电路（LV）以电路结构布置，用于读取和评估半导体存储器单元的存储状态。 在读取过程之前，通过电路（STAD）完成读取过程之后立即自动灭活的当前评估电路被自动灭活。 版权所有（C）2004，JPO

    MASTER LATCH CIRCUIT WITH SIGNAL LEVEL DISPLACEMENT FOR A DYNAMIC FLIP-FLOP
    2.
    发明申请
    MASTER LATCH CIRCUIT WITH SIGNAL LEVEL DISPLACEMENT FOR A DYNAMIC FLIP-FLOP 审中-公开
    使用信号电平切换进行动态触发器的主锁存器切换

    公开(公告)号：WO2005039050A2

    公开(公告)日：2005-04-28

    申请号：PCT/EP2004009853

    申请日：2004-09-03

    Applicant: INFINEON TECHNOLOGIES AG ,  BERTHOLD JOERG ,  GEORGAKOS GEORG ,  HENZLER STEPHAN ,  SCHMITT-LANDSIEDEL DORIS

    Inventor： BERTHOLD JOERG ,  GEORGAKOS GEORG ,  HENZLER STEPHAN ,  SCHMITT-LANDSIEDEL DORIS

    IPC: H03K3/037 ,  H03K3/356

    CPC classification number: H03K3/037 ,  H03K3/356121

    Abstract: A master latch circuit (10) with signal level displacement for a flip-flop (1) clocked by a clock pulse signal (Clk), wherein the master latch circuit (10) comprises a signal delay circuit (13) which delays and inverts the clock pulse signal (ClK), resulting in a specific time delay (AT), and a circuit node (14) which, in a charging phase wherein the clock pulse signal (Clk) is logically low, is charged to an operational voltage (VB) and which, in an evaluation phase when the clock pulse signal (Clk) and delayed, inverted clock pulse signal (ClkDELAY) are logically high, is discharged according to a specific data signal (D), wherein the data signal controls only transistors of a single type (either only N-channel or only P-channel). The master latch circuit (10) has only one supply voltage .

    Abstract translation: MasterLatchschaltung（10）具有用于一个触发器信号电平移位（1）由一个时钟信号（CLK）的时钟频率，所述MasterLatchschaltung（10），包括：信号延迟电路（13），其具有所施加的时钟信号（CLK） 一定的时间延迟（AT）延迟和倒置; 和一个电路节点（14），其在充电阶段，其中所施加的时钟信号（CLK）为逻辑低电平时，到工作电压（VB）充电，并且当所施加的时钟信号（CLK）和延迟反相在评估阶段， 时钟信号（ClkDELAY）是逻辑高时，根据所施加的数据信号（d）的可放电，其中，所述数据信号驱动仅单一类型的晶体管（N-或P-沟道只）。 主锁存电路（10）仅具有单个电源电压。

    4.
    发明专利
    未知

    公开(公告)号：ES2166114T3

    公开(公告)日：2002-04-01

    申请号：ES98103736

    申请日：1998-03-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： REINER ROBERT ,  SCHMITT-LANDSIEDEL DORIS ,  GUENGERICH VOLKER DR ,  SCHRAUD GERHARD DR

    IPC: G06K19/07 ,  H02J17/00 ,  H04B5/02

    Abstract: The data carrier is equipped with at least one coil (1) for a contactless reception of amplitude-modulated signals, a rectifier circuit (2) coupled with the coil, and a circuit arrangement (3) for processing and/or storing of data. A supply voltage regulation circuit (4) is connected in parallel with the circuit arrangement. A current measurement arrangement functioning as amplitude demodulator (SME) is arranged between the coil and the supply voltage regulation circuit. The current measurement arrangement is preferably provided by a resistance or a current mirror circuit arranged in the current path between the rectifier circuit and the supply voltage regulation circuit.

    5.
    发明专利
    未知

    公开(公告)号：DE19945434A1

    公开(公告)日：2001-04-05

    申请号：DE19945434

    申请日：1999-09-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHMITT-LANDSIEDEL DORIS ,  SCHOEBINGER MATTHIAS ,  TIHANYI JENOE ,  WURZER HELMUT ,  PLATZOEDER MICHAEL ,  SCHMID WILHELM

    IPC: H01L23/34 ,  H01L23/38 ,  H01L25/065 ,  H05K7/20

    Abstract: The invention relates to a device for cooling an integrated circuit of an electronic, preferably mobile, appliance. The device for cooling is provided with a cooling element. The integrated circuit is provided with areas, wherein the power is consumed in different manners. The inventive device is characterised in that said device is provided with at least two cooling element for selectively cooling a partial surface of the integrated circuit respectively. The temperature of heavily used or speed-determining areas of a circuit is thus specifically influenced. Different cooling elements can be controlled according to the temperature to be maintained or the current computing power of the area to be cooled respectively.

    6.
    发明专利
    未知

    公开(公告)号：BR9908478A

    公开(公告)日：2000-12-05

    申请号：BR9908478

    申请日：1999-03-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHMITT-LANDSIEDEL DORIS ,  SCHRAUD GERHARD ,  REINER ROBERT ,  GUENGERICH VOLKER

    IPC: G06K19/07 ,  H02J17/00 ,  H04B5/02

    Abstract: The data carrier is equipped with at least one coil (1) for a contactless reception of amplitude-modulated signals, a rectifier circuit (2) coupled with the coil, and a circuit arrangement (3) for processing and/or storing of data. A supply voltage regulation circuit (4) is connected in parallel with the circuit arrangement. A current measurement arrangement functioning as amplitude demodulator (SME) is arranged between the coil and the supply voltage regulation circuit. The current measurement arrangement is preferably provided by a resistance or a current mirror circuit arranged in the current path between the rectifier circuit and the supply voltage regulation circuit.

    9.
    发明专利
    未知

    公开(公告)号：DE102004036956B3

    公开(公告)日：2006-03-23

    申请号：DE102004036956

    申请日：2004-07-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HENZLER STEPHAN ,  BERTHOLD JOERG ,  GEORGAKOS GEORG ,  SCHMITT-LANDSIEDEL DORIS

    IPC: H03K19/00 ,  H03K19/094

    Abstract: Logic activation circuit for switching a logic circuit having at least one supply voltage line on or off, said logic activation circuit having: (a) at least one voltage supply switching device for connecting a supply voltage to a supply voltage line of the logic circuit in a manner dependent on a changeover control signal that is applied to a control terminal of the voltage supply switching device; and having (b) a charge equalization switching device which, in a manner dependent on a control switching pulse, connects the supply voltage line of the logic circuit to the control terminal of the voltage supply switching device for the duration of the control switching pulse so that charge equalization is effected between the supply voltage line and the control terminal of the voltage supply switching device in order to generate the changeover control signal.

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