公开(公告)号：DE50111772D1

公开(公告)日：2007-02-15

申请号：DE50111772

申请日：2001-05-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRASS ECKHARD DR ,  SCHAFFROTH THILO ,  SCHNABEL JOACHIM ,  SCHNEIDER HELMUT

IPC: G01R31/28 ,  G11C29/00 ,  G11C11/401 ,  G11C29/12 ,  G11C29/26 ,  H01L27/10

Abstract: A method for testing a multiplicity of word lines of a semiconductor memory configuration in a multiple word line wafer test is described. To prevent a pulling-up of inactive word lines which are at a negative voltage when the active word lines are ramped down, the inactive word lines are decoupled from the negative word line voltage and are connected to a high impedance shortly before the active word lines are ramped down.