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    INTEGRATED SEMICONDUCTOR CIRCUIT COMPRISING A PARALLEL CONNECTION OF COUPLED CAPACITORS
    1.
    发明申请
    INTEGRATED SEMICONDUCTOR CIRCUIT COMPRISING A PARALLEL CONNECTION OF COUPLED CAPACITORS 审中-公开
    与并行耦合容量集成半导体电路

    公开(公告)号：WO03073510A2

    公开(公告)日：2003-09-04

    申请号：PCT/DE0300547

    申请日：2003-02-21

    Applicant: INFINEON TECHNOLOGIES AG ,  BRENNER PIETRO

    Inventor： BRENNER PIETRO

    IPC: H01L27/08 ,  H01L29/94

    CPC classification number: H01L27/0811 ,  H01L29/94

    Abstract: The invention relates to an integrated semiconductor circuit (1) provided with capacitors (10, 20), each of which having a first electrode (11, 21), a second electrode (12, 22) with a doped layer (13, 23), and a dielectric (14, 24). The poly-depletion effect of the doped layers used leads to a distortion of the capacitance characteristic curve whereby traditionally requiring each capacitor (10, 20) to have a supplementary circuit for correcting the characteristic curve. The prior art already provides a parallel connection of two capacitors (10, 20), which have a largely linear capacitance-voltage characteristic curve and, therefore, are used without the provision of linearizing supplementary circuits. According to the invention, the areas (A1, A2) of doped layers (13, 23) of both capacitors (10, 20) have different dimensions, whereby an even greater linearization of the capacitance-voltage characteristic curve is attained without the connection of any additional capacitors.

    Abstract translation: 本发明涉及一种半导体集成电路（1），所述电容器（10，20）各具有与掺杂掺杂层（13，23）和第一电极（11，21），第二电极（12，22） Dielek trikum（14，24）。 掺杂层的多晶硅耗尽效应用于通向电容特性曲线的失真，这就是为什么传统的，每个电容器（10，20），需要用于校正特性曲线的附加电路。 已知的有两个电容器（10，20），其具有一个基本上线性电容 - 电压特性，因此无需额外的线性化电路中使用的并联连接。 根据本发明，基区域的（Al，A2）被掺杂不同尺寸，由此在不添加电路的任何进一步的电容器实现的电容 - 电压特性的更大的线性化的层（13，23）两个电容器（10，20）。

    SEMICONDUCTOR ARRANGEMENT AND METHOD FOR PRODUCTION THEREOF
    2.
    发明申请
    SEMICONDUCTOR ARRANGEMENT AND METHOD FOR PRODUCTION THEREOF 审中-公开
    半导体器件和方法及其

    公开(公告)号：WO0217399A8

    公开(公告)日：2002-05-02

    申请号：PCT/DE0102701

    申请日：2001-07-18

    Applicant: INFINEON TECHNOLOGIES AG ,  BRENNER PIETRO

    Inventor： BRENNER PIETRO

    IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/762 ,  H01L23/64 ,  H01L21/02

    CPC classification number: H01L21/76224 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The invention relates to a semiconductor arrangement with a substrate, comprising at last one component integrated therein and on the main side of which a metallisation is provided. At least parts of the metallisation are provided with an underlying insulation layer lying in the substrate. Parasitic capacitances and undesired signal power losses for high frequency signals can be reduced as the insulation layer is in the form of a trench grid.

    Abstract translation: 本发明提出一种半导体器件，包括具有至少一个内置的部件的基板和金属化被提供其第一页上。 在金属化的至少部分是与垫层位于衬底的绝缘层。 其特征在于，所述绝缘层是在沟槽栅格的形式来实现，寄生电容和不希望的信号的功率损失可在高频信号被减小。

    4.
    发明专利
    未知

    公开(公告)号：DE10041691A1

    公开(公告)日：2002-03-14

    申请号：DE10041691

    申请日：2000-08-24

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BRENNER PIETRO

    IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/762 ,  H01L23/522 ,  H01L23/66

    Abstract: The invention relates to a semiconductor arrangement with a substrate, comprising at last one component integrated therein and on the main side of which a metallisation is provided. At least parts of the metallisation are provided with an underlying insulation layer lying in the substrate. Parasitic capacitances and undesired signal power losses for high frequency signals can be reduced as the insulation layer is in the form of a trench grid.

    5.
    发明专利
    未知

    公开(公告)号：AT431966T

    公开(公告)日：2009-06-15

    申请号：AT01962562

    申请日：2001-07-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BRENNER PIETRO

    IPC: H01L23/52 ,  H01L23/64 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/762

    Abstract: The invention proposes a semiconductor configuration having a substrate, which has at least one component integrated therein. The substrate has a first main side with a metalization. At least parts of the metalization are underlaid with an insulation layer located in the substrate. By virtue of the fact that the insulation layer is realized in the form of a trench lattice, it is possible to reduce parasitic capacitances and undesirable signal power losses in the case of high-frequency signals.

    Vorrichtungen mit koax-ähnlichen elektrischen Verbindungen und Verfahren zu deren Herstellung
    9.
    发明专利
    Vorrichtungen mit koax-ähnlichen elektrischen Verbindungen und Verfahren zu deren Herstellung 未知

    公开(公告)号：DE102020122073A1

    公开(公告)日：2022-02-24

    申请号：DE102020122073

    申请日：2020-08-24

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KALEEM SAQIB ,  DECHANT MARTIN ,  BRENNER PIETRO ,  FRITZIN JONAS ERIC SEBASTIAN

    IPC: H01L23/485 ,  H01L21/60

    Abstract: Eine Vorrichtung enthält einen Halbleiterchip mit einem elektrischen Kontakt, der auf einer Hauptoberfläche des Halbleiterchips angeordnet ist. Die Vorrichtung enthält ein externes Verbindungselement, das dazu ausgelegt ist, eine erste koax-ähnliche elektrische Verbindung zwischen der Vorrichtung und einer Leiterplatte bereitzustellen, wobei die erste koax-ähnliche elektrische Verbindung einen Abschnitt aufweist, der sich in einer Richtung senkrecht zur Hauptoberfläche des Halbleiterchips erstreckt. Die Vorrichtung enthält ferner eine elektrische Umverteilungsschicht, die über der Hauptoberfläche des Halbleiterchips angeordnet und dazu ausgelegt ist, eine zweite koax-ähnliche elektrische Verbindung zwischen dem elektrischen Kontakt des Halbleiterchips und dem externen Verbindungselement bereitzustellen, wobei die zweite koax-ähnliche elektrische Verbindung einen Abschnitt aufweist, der sich in einer Richtung parallel zur Hauptoberfläche des Halbleiterchips erstreckt.

    10.
    发明专利
    未知

    公开(公告)号：DE50114903D1

    公开(公告)日：2009-07-02

    申请号：DE50114903

    申请日：2001-07-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BRENNER PIETRO

    IPC: H01L23/52 ,  H01L23/64 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/762

    Abstract: The invention proposes a semiconductor configuration having a substrate, which has at least one component integrated therein. The substrate has a first main side with a metalization. At least parts of the metalization are underlaid with an insulation layer located in the substrate. By virtue of the fact that the insulation layer is realized in the form of a trench lattice, it is possible to reduce parasitic capacitances and undesirable signal power losses in the case of high-frequency signals.

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