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    1.
    发明专利
    未知

    公开(公告)号：DE50006865D1

    公开(公告)日：2004-07-29

    申请号：DE50006865

    申请日：2000-04-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BROX DR ,  PFEFFERL KARL-PETER

    IPC: G06F12/16 ,  G06F11/20 ,  G11C11/401 ,  G11C11/409 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

    Abstract: The memory has data lines (MDQii) which are connected to the local data lines located in the storage cell array. The data lines (MDQii) are compiled into groups (U1-U8) and at least one group, or discrete data lines of the groups, are formed by redundant data lines (MDQiiR), and are connected to the input/output (IO) lines leading out from the memory into the groups (IO1-IO4). A bus system arranged into at least two planes is provided and in which a first plane has available bus lines (Ai) which are connectable, on the one hand, to all IO lines (RWDii) and on the other hand, to the data lines (MDQii), and has a second plane of several separate part buses (B1-B4), whose bus lines (Bii) are connected on one side, to data lines (MDQii) of at least two groups of data lines (Qi), and on the other side, to the IO lines (RWDii) of one group (IO).

    2.
    发明专利
    未知

    公开(公告)号：DE59912917D1

    公开(公告)日：2006-01-19

    申请号：DE59912917

    申请日：1999-09-01

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LE THOAI-THAI ,  BROX DR ,  LINDOLF DR ,  BRASS DR

    IPC: G11C11/407 ,  G11C5/14 ,  G11C8/00 ,  G11C8/08 ,  G11C11/401

    Abstract: An integrated semiconductor storage device includes a number of memory or storage cells (13-15) arranged in at least two sections (1-4) of which each section is supplied by a supply potential (at 12,22,32,42). A supply voltage source (10,20,30,40) is provided for each of the sections, and a decoder (5) provides an output signal for each of the sections (1) for activating and deactivating the respective section (1) for memory storage access. The supply voltage sources (10) are controlled so that the supply potential is made available with higher driver capability for one of the sections (1), when this section (1) is activated by the respective output signal (A11), and with lower driver capability when this section is deactivated by the respective output signal (A11).

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