公开(公告)号：JP2002050639A

公开(公告)日：2002-02-15

申请号：JP2001183760

申请日：2001-06-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CURELLO GIUSEPPE ,  KIESLICH ALBRECHT

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a simple and inexpensive method for manufacturing a field effect transistor, having a high switching speed. SOLUTION: An injection step using high energy and a small amount of dose is added, thus providing the method for manufacturing the field effect transistor, where the capacity at a p-n junction part between a source and/or the drain and the substrate is reduced. The reduced capacity at the p-n junction part accelerates the switching sped of the transistor. At that time, the method can be easily integrated into the existing manufacturing method of the field effect transistor.

公开(公告)号：DE10142307A1

公开(公告)日：2003-03-27

申请号：DE10142307

申请日：2001-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CAPPELLANI ANNALISA ,  CURELLO GIUSEPPE ,  SCHUMANN DIRK

IPC: H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/06

Abstract: A depression is produced into the channel region (2-3) of the semiconductor substrate (2-0). This lies below surrounding regions of the substrate. A gate insulator (2-24) is produced on the surface of the channel region and a gate electrode (2-26) is then deposited upon it. In immediately surrounding regions of the substrate, diffused regions are produced to form the source (2-52) and drain (2-53).

公开(公告)号：DE10062494A1

公开(公告)日：2002-05-29

申请号：DE10062494

申请日：2000-12-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CURELLO GIUSEPPE

IPC: H01L21/265 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/336 ,  H01L21/8234

Abstract: Production of spacer oxide layers on the side walls of field effect transistors comprises forming control electrodes (5c, 5d, 5e) made from polysilicon on a semiconductor substrate (1), each electrode separated from the substrate by a gate oxide (4c, 4d, 4e); implanting ions into the side walls of the electrodes to increase the oxidation rate of the polysilicon; and thermally oxidizing the implanted electrodes at a defined temperature to form spacer oxide layers. Preferred Features: The ions are implanted into the electrodes at an angle ( alpha ) with respect to the side walls. The electrodes have a defined height (H) and distance (A) from each other. The implanting ions are fluorine and/or argon.

公开(公告)号：DE10131710B4

公开(公告)日：2006-05-18

申请号：DE10131710

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AMON JUERGEN ,  TRUEBY ALEXANDER ,  CURELLO GIUSEPPE

IPC: H01L21/762

公开(公告)号：DE10142307B4

公开(公告)日：2004-12-30

申请号：DE10142307

申请日：2001-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CAPPELLANI ANNALISA ,  CURELLO GIUSEPPE ,  SCHUMANN DIRK

IPC: H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/06

公开(公告)号：DE10131710A1

公开(公告)日：2003-01-30

申请号：DE10131710

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AMON JUERGEN ,  TRUEBY ALEXANDER ,  CURELLO GIUSEPPE

IPC: H01L21/762

Abstract: Process for adjusting height of step between active and insulating regions during production of integrated circuits comprises: etching trenches (6) filled with oxide (8') in a semiconductor substrate (1) to isolate active regions; and implanting electrically non-active element into oxide (8') in partial region (II) of semiconductor wafer to change etching rate of oxide in the partial region. An Independent claim is also included for a process for the production of a dynamic random access memory (DRAM) semiconductor memory.

公开(公告)号：DE10029659A1

公开(公告)日：2002-01-03

申请号：DE10029659

申请日：2000-06-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KIESLICH ALBRECHT ,  CURELLO GIUSEPPE

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L29/78

Abstract: Production of a field effect transistor (FET) comprises: (a) preparing a substrate (1) having a surface layer (7) made of a material of first conductivity; (b) forming a gate oxide; (c) applying a gate electrode; (d) carrying out a first implantation step to form a source/drain region using a doping material of second conductivity; and (e) carrying out a second implantation step using a doping material of second conductivity so that the capacity of the pn-junction of the source/drain region to the substrate is reduced. Preferred Features: The capacity of the pn-junction of the source/drain region to the substrate is reduced by at least 3, preferably at least 5%. Masking of the source/drain region is the same in the two implantation steps. The doping materials are the same.