公开(公告)号：WO02086967A3

公开(公告)日：2003-09-25

申请号：PCT/EP0204308

申请日：2002-04-18

Applicant: INFINEON TECHNOLOGIES AG ,  STAUB RALF ,  AMON JUERGEN ,  URBANSKY NORBERT

Inventor： STAUB RALF ,  AMON JUERGEN ,  URBANSKY NORBERT

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/108 ,  H01L21/283

CPC classification number: H01L21/76808 ,  H01L21/28512 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/10829 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/905

Abstract: According to the invention, a contact hole is filled with a metal or a metal alloy when a bit line is brought into contact with a selection transistor of a dynamic memory unit on a semiconductor wafer. The semiconductor substrate in the contact hole comprises a dopant, and a liner layer is integrated between the semiconductor substrate and the metal filling.

Abstract translation: 根据本发明，配备有动态存储器单元的半导体晶片上的选择晶体管设置填充有金属或在与位线相接触的金属合金的接触孔，所述接触孔的半导体基板的掺杂和引入的半导体基板和金属填充物之间的衬垫层 是。

公开(公告)号：DE10250872A1

公开(公告)日：2004-05-19

申请号：DE10250872

申请日：2002-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AMON JUERGEN ,  FAUL JUERGEN ,  GRUENING ULRIKE ,  JAKUBOWSKI FRANK ,  SCHUSTER THOMAS ,  STRASSER RUDOLF

IPC: H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242

Abstract: Gate stacks (GS1-4) are applied to a gate dielectric (11) over the semiconductor substrate (10). A sidewall oxide (17) is formed on the gate stacks. A mask (12) is applied to the semiconductor structure, and is then structured. A contact doping (13) is implanted and self-adjusts to the sidewall oxide of the gate stack (GS1, GS2), in regions not covered by the mask

公开(公告)号：DE10131710B4

公开(公告)日：2006-05-18

申请号：DE10131710

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AMON JUERGEN ,  TRUEBY ALEXANDER ,  CURELLO GIUSEPPE

IPC: H01L21/762

公开(公告)号：DE10153200B4

公开(公告)日：2005-08-04

申请号：DE10153200

申请日：2001-10-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AMON JUERGEN ,  FAUL JUERGEN ,  SCHUSTER THOMAS ,  STAUB RALF

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/316

公开(公告)号：DE10228571A1

公开(公告)日：2004-01-22

申请号：DE10228571

申请日：2002-06-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AMON JUERGEN ,  FAUL JUERGEN ,  SCHUSTER THOMAS ,  RUDER THOMAS

IPC: H01L21/60 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/04 ,  H01L29/10 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

Abstract: A semiconductor structure having a plurality of gate stacks on a semiconductor substrate provided with a gate dielectric. The gate stacks have a lower first layer made of polysilicon, an overlying second layer made of a metal silicide, and an upper third layer made of an insulating material, and a sidewall oxide on the sidewalls of the first and second layers. The sidewall oxide is thinned or removed on one of the sidewalls, and the gate stacks have sidewall spacers made of the insulating material.

公开(公告)号：DE19939597B4

公开(公告)日：2006-07-20

申请号：DE19939597

申请日：1999-08-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KIESLICH ALBRECHT ,  AMON JUERGEN

IPC: H01L21/762

Abstract: A method for fabricating a microelectronic structure includes implanting nitrogen into a semiconductor substrate which is provided with trenches, at least in the region of a main area of the semiconductor substrate. The implantation is intended to be carried out in such a way that a nitrogen concentration at the main area is considerably greater than at the side walls of the trenches. As a result, during subsequent oxidation of the semiconductor substrate, a thinner oxide layer can be formed on the main area, in comparison with the side walls. The oxide layer has a homogeneous transition in the edge region between the main area and the side walls. Implanting nitrogen prior to the oxidation of the semiconductor substrate leads to a uniform oxide layer thickness on the main area.

公开(公告)号：DE10356476B3

公开(公告)日：2005-06-30

申请号：DE10356476

申请日：2003-12-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AMON JUERGEN ,  FAUL JUERGEN ,  SCHUSTER THOMAS ,  MUELLER RALF ,  KIESLICH ALBRECHT ,  ALSMEIER JOHANN ,  OFFENBERG DIRK ,  GOLDBACH MATTHIAS

IPC: H01L27/108 ,  H01L21/265 ,  H01L21/8242

Abstract: A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.

公开(公告)号：DE10250872B4

公开(公告)日：2005-04-21

申请号：DE10250872

申请日：2002-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AMON JUERGEN ,  FAUL JUERGEN ,  GRUENING ULRIKE ,  JAKUBOWSKI FRANK ,  SCHUSTER THOMAS ,  STRASSER RUDOLF

IPC: H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242

Abstract: Gate stacks (GS1-4) are applied to a gate dielectric (11) over the semiconductor substrate (10). A sidewall oxide (17) is formed on the gate stacks. A mask (12) is applied to the semiconductor structure, and is then structured. A contact doping (13) is implanted and self-adjusts to the sidewall oxide of the gate stack (GS1, GS2), in regions not covered by the mask

公开(公告)号：DE10121011A1

公开(公告)日：2002-11-14

申请号：DE10121011

申请日：2001-04-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AMON JUERGEN ,  WURZER HELMUT

IPC: H01L21/768 ,  H01L21/8242

Abstract: Process for doping bit line contact holes comprises simultaneously opening contact holes (5) in the cell field and also further contact holes in peripheral circuits of the chip; and carrying out unmasked n-type doping of all the contact holes. An Independent claim is also included for a semiconductor arrangement with contact holes. Preferred Features: In a previous step, an n-type implantation does in the drain/source doping of the contact holes in the peripheral circuits corresponding to the unmasked n-type doping is reduced. The bit line contact (CB) is filled with tungsten.

公开(公告)号：DE10121011B4

公开(公告)日：2004-11-04

申请号：DE10121011

申请日：2001-04-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AMON JUERGEN ,  WURZER HELMUT

IPC: H01L21/768 ,  H01L21/8242 ,  H01L27/108