公开(公告)号：WO0241399A3

公开(公告)日：2002-08-15

申请号：PCT/EP0112034

申请日：2001-10-17

Applicant: INFINEON TECHNOLOGIES AG ,  MOLL HANS-PETER ,  WICH-GLASEN ANDREAS ,  TRUEBY ALEXANDER

Inventor： MOLL HANS-PETER ,  WICH-GLASEN ANDREAS ,  TRUEBY ALEXANDER

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  Y10S438/928 ,  Y10S438/976

Abstract: The invention relates to a method for producing an integrated semiconductor component (1). At least one isolation trench is formed, a first layer (4) consisting of a non-conductive material is applied by means of a non-conforming deposition process, and a second layer (5) consisting of a non-conductive material is applied at least to the rear side of the semiconductor component by means of a conforming deposition process.

Abstract translation: 本发明公开了用于制造集成半导体器件1，其中，在形成至少一个隔离沟槽的方法中，第一层4由非导电材料由一非共形沉积方法，并通过非导电材料的第二层5涂覆 共形沉积方法，至少施加到半导体器件的背面。

公开(公告)号：DE59803426D1

公开(公告)日：2002-04-25

申请号：DE59803426

申请日：1998-12-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  OTANI DR ,  SCHLOESSER DR ,  WEINRICH DR ,  RUSCH ANDREAS ,  TRUEBY ALEXANDER ,  HAIN MANFRED ,  ZIMMERMANN DR ,  KOHLHASE DR

IPC: H01L21/8247 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: The memory cell arrangement has several ferroelectric memory cells (S) provided in a semiconductor substrate (10). Parallel bit line grooves (1a-1e) run in the longitudinal direction in the main surface of the substrate. A bit line (15a-15d) is provided in the base of each groove. A source drain region (25a-25d) is provided at the ridge of each groove. A channel region is provided in the walls of each groove. The channel regions are provided in one groove wall, such that a controllable switching transistor for selecting the respective memory cell is formed, while the channel region in the other wall is arranged such that the respective transistor is off. Insulated word lines are provided in the transverse direction along the main surface of the substrate through the bit line grooves, to control the selection transistors. Insulation grooves (3a-3c) run in the transverse direction in the main surface of the substrate to insulate the source/drain regions of adjacent memory cells. A ferroelectric capacitor is connected to each source/drain region of respective memory cell (s) above the word lines (2a-2d).

公开(公告)号：DE10131710A1

公开(公告)日：2003-01-30

申请号：DE10131710

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AMON JUERGEN ,  TRUEBY ALEXANDER ,  CURELLO GIUSEPPE

IPC: H01L21/762

Abstract: Process for adjusting height of step between active and insulating regions during production of integrated circuits comprises: etching trenches (6) filled with oxide (8') in a semiconductor substrate (1) to isolate active regions; and implanting electrically non-active element into oxide (8') in partial region (II) of semiconductor wafer to change etching rate of oxide in the partial region. An Independent claim is also included for a process for the production of a dynamic random access memory (DRAM) semiconductor memory.

公开(公告)号：DE59914831D1

公开(公告)日：2008-09-25

申请号：DE59914831

申请日：1999-03-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUSCH ANDREAS ,  ROTHENHAEUSSER STEFFEN ,  TRUEBY ALEXANDER ,  OTANI YOICHI ,  ZIMMERMANN ULRICH

IPC: H01L27/112 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10

Abstract: A method for fabricating a semiconductor memory device is described. An insulating layer is disposed on a semiconductor substrate. A matrix of semiconductor memory elements is disposed in the substrate. The semiconductor memory elements include a plurality of contact holes formed in the insulating layer. One contact hole is formed in the insulating layer for each of the semiconductor memory elements. A bit definition region is disposed in the semiconductor substrate underneath each of the contact holes. A contact plug is disposed in each of the contact holes and is in electrical contact with the bit definition region. The bit definition region is configured such that a contact resistance between the semiconductor substrate and the contact plug defines a bit to be stored in the semiconductor memory elements, An evaluation circuit is connected to and evaluates the contact resistance of the semiconductor memory elements.

公开(公告)号：DE10127622A1

公开(公告)日：2002-12-19

申请号：DE10127622

申请日：2001-06-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TRUEBY ALEXANDER ,  WICH-GLASEN ANDREAS ,  MOLL HANS-PETER

IPC: H01L21/762

Abstract: The production of an HDPCVD oxide-filled insulation trench comprises forming an insulation trench in a semiconductor substrate (60); forming a first silicon oxide layer (66) on the side walls and on the base of the trench by oxidizing; forming a second silicon oxide layer (68) on the side walls and on the base of the trench using an HDPCVD process; and depositing a third silicon oxide layer by HDPCVD so that the trench is filled with silicon oxide. Preferred Features: The insulation trench is 300-500, preferably 350-450 microns m deep and less than 0.3, preferably less then 0.2 microns m wide. The second oxide layer is 20-200, preferably 40-150 nm thick. The third oxide layer is 300-500, preferably 350-450 nm thick. The silicon source in the HDPCVD process is tetraethylorthosilicate.

公开(公告)号：DE10056261A1

公开(公告)日：2002-05-29

申请号：DE10056261

申请日：2000-11-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TRUEBY ALEXANDER ,  WICH-GLASEN ANDREAS ,  MOLL HANS-PETER

IPC: H01L21/762

Abstract: The invention relates to a method for producing an integrated semiconductor component (1). At least one isolation trench is formed, a first layer (4) consisting of a non-conductive material is applied by means of a non-conforming deposition process, and a second layer (5) consisting of a non-conductive material is applied at least to the rear side of the semiconductor component by means of a conforming deposition process.

公开(公告)号：DE50114133D1

公开(公告)日：2008-08-28

申请号：DE50114133

申请日：2001-10-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MOLL HANS-PETER ,  WICH-GLASEN ANDREAS ,  TRUEBY ALEXANDER

IPC: H01L21/762

Abstract: A method for the fabrication of an integrated semiconductor component, in which at least one isolation trench is formed, a first layer of a nonconductive material is applied by a nonconformal deposition method, and a second layer of a nonconductive material is applied by a conformal deposition method at least to the back surface of the semiconductor component.

公开(公告)号：DE10131710B4

公开(公告)日：2006-05-18

申请号：DE10131710

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AMON JUERGEN ,  TRUEBY ALEXANDER ,  CURELLO GIUSEPPE

IPC: H01L21/762

公开(公告)号：DE10123509A1

公开(公告)日：2002-11-28

申请号：DE10123509

申请日：2001-05-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOLLATZ MARK ,  TRUEBY ALEXANDER ,  TOEBBEN DIRK ,  MORHARD KLAUS-DIETER

IPC: H01L21/3105 ,  H01L21/762 ,  H01L21/8242

Abstract: The method involves applying a layer to be planarized over the semiconducting structure with recesses corresponding to trench regions. The substructures have a second sub-structure with second trench regions and the applied layer has further recesses above the second trench regions. A pre- planarizing mask masks a second area on the layer to be planarized above the second sub-structure.

公开(公告)号：DE19815874C2

公开(公告)日：2002-06-13

申请号：DE19815874

申请日：1998-04-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUSCH ANDREAS ,  OTANI YOICHI ,  ROTHENHAEUSER STEFFEN ,  TRUEBY ALEXANDER ,  ZIMMERMANN ULRICH

IPC: H01L21/822 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/112

Abstract: A method for fabricating a semiconductor memory device is described. An insulating layer is disposed on a semiconductor substrate. A matrix of semiconductor memory elements is disposed in the substrate. The semiconductor memory elements include a plurality of contact holes formed in the insulating layer. One contact hole is formed in the insulating layer for each of the semiconductor memory elements. A bit definition region is disposed in the semiconductor substrate underneath each of the contact holes. A contact plug is disposed in each of the contact holes and is in electrical contact with the bit definition region. The bit definition region is configured such that a contact resistance between the semiconductor substrate and the contact plug defines a bit to be stored in the semiconductor memory elements, An evaluation circuit is connected to and evaluates the contact resistance of the semiconductor memory elements.