中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.022 seconds)

    Forming alignment mask for semiconductor memory unit, includes stages of electrode formation, dielectric deposition, selective filling, collar- and hollow formation
    2.
    发明专利
    Forming alignment mask for semiconductor memory unit, includes stages of electrode formation, dielectric deposition, selective filling, collar- and hollow formation 未知

    公开(公告)号：DE102004002205B3

    公开(公告)日：2005-06-23

    申请号：DE102004002205

    申请日：2004-01-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SEITZ MIHEL ,  SACHSE HERMANN ,  MOLL HANS-PETER ,  FROEHLICH HANS-GEORG ,  VOIGT INA

    IPC: H01L21/8242 ,  H01L23/544

    Abstract: A semiconductor wafer with substrate (5) is prepared. A deep trench (12) and at least one depression are formed in the substrate. An external capacitor electrode is formed in the lower region of the trench (12). Dielectric is deposited in the lower region of the trench. An inner capacitor electrode is formed by filling the lower region only, with conductive material. A collar (42) is formed in the upper region of the side walls of the trench and the depression. Trench and depression are filled in the upper region with filling material (48), so that in the region of the depression a hollow representing the alignment mask remains. A semiconductor wafer with substrate (5) is prepared. A deep trench (12) and at least one depression are formed in the substrate. An external capacitor electrode is formed in the lower region of the trench (12). Dielectric is deposited in the lower region of the trench. An inner capacitor electrode is formed by filling the lower region only, with conductive material. A collar (42) is formed in the upper region of the side walls of the trench and the depression. Trench and depression are filled in the upper region with filling material (48), so that in the region of the depression a hollow representing the alignment mask remains. A liner layer (16) is deposited completely over the whole area of the substrate (5). Full-area deposition of a non-doped amorphous silicon layer follows, over the liner layer. A resist layer is deposited over the non-doped amorphous silicon layer. The resist layer is structured so that the upper side of the semiconductor wafer is covered by it, in the region of the hollow. Angled implantation of a dopant follows, forming a doped amorphous silicon layer. The resist layer is removed. Selective etching of the non-doped amorphous silicon layer, bares the underlying liner layer. This is then removed and the filling material in the trench and in the depression is etched. An independent claim is included for the corresponding semiconductor arrangement with alignment mask and trench capacitor.

    5.
    发明专利
    未知

    公开(公告)号：DE10141485A1

    公开(公告)日：2003-03-13

    申请号：DE10141485

    申请日：2001-08-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KIESLICH ALBRECHT ,  SACHSE HERMANN

    IPC: G03F1/00 ,  G03F1/14

    Abstract: A mask for fabricating semiconductor components contains first transparent regions and second transparent regions. The second regions are laid out such that they do not act on the regions of the photoresist directly beneath them in the exposure of the photoresist through the mask. The transparent regions define a size and a shape of structures to be formed.

Patent Agency Ranking