公开(公告)号：DE10141025A1

公开(公告)日：2003-03-13

申请号：DE10141025

申请日：2001-08-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREBNER THOMAS ,  SCHITTENHELM MICHAEL ,  OSTENDORF HANS-CHRISTOPH ,  THALMANN ERWIN

IPC: G01R31/28 ,  G01R35/00 ,  H01L21/66

Abstract: A process for testing wafers in a test machine which can be calibrated automatically places a calibrating wafer (107) in the machine, calibrates it by means of a control unit and then inserts the wafer to be tested into the calibrated machine. An Independent claim is also included for a calibrating wafer for the above process.

公开(公告)号：DE10141025B4

公开(公告)日：2007-05-24

申请号：DE10141025

申请日：2001-08-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREBNER THOMAS ,  SCHITTENHELM MICHAEL ,  OSTENDORF HANS-CHRISTOPH ,  THALMANN ERWIN

IPC: H01L21/66 ,  G01R31/28 ,  G01R35/00

Abstract: The invention provides a method for testing wafers ( 101 ) to be tested in a test device ( 100 ), in which the test device ( 100 ) can be calibrated, at least one calibration wafer ( 102 ) being automatically introduced into the test device ( 100 ) by means of a handling unit ( 103 ), calibration values of the test device ( 100 ) being determined by means of a control by a calibration sequence control unit ( 105 ), the calibration values determined being stored in a memory unit ( 106 ), the test device ( 100 ) being calibrated by means of the stored calibration values, the calibration wafer ( 102 ) being output from the calibrated test device ( 100 ), and at least one wafer ( 101 ) to be tested being introduced into the calibrated test device ( 100 ) by means of the handling unit ( 103 ) and being tested by a control by means of a test sequence control unit ( 104 ) in the calibrated test device ( 100 ), the stored calibration values being applied.

公开(公告)号：DE10131712A1

公开(公告)日：2003-01-16

申请号：DE10131712

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREBNER THOMAS ,  THALMANN ERWIN

IPC: G01R31/319 ,  G01R35/00 ,  G01R31/26 ,  G01R31/28

Abstract: The calibration component has a signal input (E), to which a tester channel to be calibrated is connected. The phase difference circuit (1) is connected to the periodic signal input and a reference clock (CLK) signal. The resultant phase difference output to a tester (20). The tester has a delay device, to delay signals transmitted to the tester based on the phase difference.