公开(公告)号：WO03028044A2

公开(公告)日：2003-04-03

申请号：PCT/DE0203284

申请日：2002-09-05

Applicant: INFINEON TECHNOLOGIES AG ,  BARCHMANN BERND ,  HEINEMANN ERIK ,  HEITZER JOSEF ,  PUESCHNER FRANK

Inventor： BARCHMANN BERND ,  HEINEMANN ERIK ,  HEITZER JOSEF ,  PUESCHNER FRANK

IPC: G06K19/077 ,  H01L23/498 ,  H05K1/00 ,  H05K3/00 ,  H01C

CPC classification number: H05K3/0097 ,  G06K19/07743 ,  H01L23/49855 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0393 ,  H05K2201/09781 ,  H05K2201/2009 ,  H05K2203/1545 ,  H01L2924/00

Abstract: The invention relates to a non-conductive substrate forming a strip or a panel, on which a plurality of carrier elements, especially for installation in a chip card, are configured, said carrier elements being formed by a respective border line. Said substrate has a contact face and opposite said contact face an insertion face. The insertion face is provided with a conductive insertion face plating and said insertion face plating is configured in such a manner that the contacts of an integrated circuit to be applied to the insertion face later on and the insertion face plating are electrically contacted by a flip-chip connection.

Abstract translation: 它提出了一种非导电性，磁带，或在其上的芯片卡中形成多个载体元件，特别是用于安装一形成利益衬底，其分别由边界线，该基板具有一个接触侧和接触侧相对的插入件侧形成 ，其中所述输入侧设置有导电插入侧金属化和插入侧被形成为使得接触点之间的电连接将在后面施加到插入侧集成电路的插入侧，并且可以通过倒装芯片接合的手段来进行。

公开(公告)号：WO2004084303A3

公开(公告)日：2004-12-23

申请号：PCT/DE2004000504

申请日：2004-03-12

Applicant: INFINEON TECHNOLOGIES AG ,  HEINEMANN ERIK ,  PUESCHNER FRANK

Inventor： HEINEMANN ERIK ,  PUESCHNER FRANK

IPC: G06K19/077 ,  H01L21/56 ,  H01L23/485 ,  H01L23/498

CPC classification number: H01L24/10 ,  G06K19/07745 ,  G06K19/07747 ,  H01L21/563 ,  H01L23/49855 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012

Abstract: An arrangement with a substrate carrier (S) comprising a first surface (O1) on which outer contact elements (AK) are disposed, a second opposite surface (O2) on which chip contact elements are disposed, whereby the contact elements of the two surfaces are electrically interconnected (D) through the substrate (S), and a chip (IC), whereby the side (K) which is provided with contact points (B) faces the second surface and is electrically connected to the chip contact elements (CK) and whereby the thickness (D2) of the chip is greater than the thickness of the substrate (S). The contact points (B) of the chip (IC) are made of a metal which has a different degree of hardness than that of the chip contact elements (CK).

Abstract translation: 装置，其包括具有第一表面（01）到外接触元件（AK）的衬底支撑件（S）被安装，在芯片接触元件（CK）的第二相对表面（O2）被安装，其特征在于，两个表面的接触元件（通过基片 S）被传递电连接到彼此（D）和其（与接触点B）面向所述第二表面设置侧（K）的芯片（IC），和（与芯片接触元件CK）被电连接，并且WOEI厚度（ 模具的D2）比基板（S）的厚度大。 芯片（IC）的接触点（b）为具有具有不同程度的硬度的接触元件的芯片（CK）的金属形成。

公开(公告)号：WO0154193A3

公开(公告)日：2002-02-14

申请号：PCT/DE0100156

申请日：2001-01-16

Applicant: INFINEON TECHNOLOGIES AG ,  HEINEMANN ERIK ,  HOUDEAU DETLEF ,  PUESCHNER FRANK

Inventor： HEINEMANN ERIK ,  HOUDEAU DETLEF ,  PUESCHNER FRANK

IPC: G06K19/077 ,  H01L23/498

CPC classification number: H01L23/49855 ,  G06K19/077 ,  G06K19/07745 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265

Abstract: The invention relates to a flat support, especially for a chip module for use in chip cards. Said flat support has a first main side and a second main side. A number of first metallic coatings are provided on the first main side, with a corresponding number of second metallic coatings being provided on the second main side. The lateral recesses in the flat support are dimensioned in such a way that the flat support can be processed further by an SMD assembly machine. As a result, it is possible to use advantageous materials and current working methods. It is also possible to achieve a very high throughput with an SMD assembly machine.

Abstract translation: 本发明提出一种扁平的支持，特别是用于在芯片卡中使用的芯片模块，具有第一和在前面的第二主侧，其中多个第一金属化层和所述第二主侧的是设置在第一主第二金属的相应数量 ， 扁平载体的横向凹部尺寸，使得表面积载体可以由SMD贴片机进行进一步处理。 这允许使用廉价的材料和标准作业程序是可能的。 在另一方面，具有非常高的吞吐量可以用SMD贴片机来实现。

公开(公告)号：WO03085727A2

公开(公告)日：2003-10-16

申请号：PCT/DE0301149

申请日：2003-04-08

Applicant: INFINEON TECHNOLOGIES AG ,  BEYER VOLKER ,  FISCHER JUERGEN ,  HEINEMANN ERIK ,  MARBACH-FISCHBACH IDA

Inventor： BEYER VOLKER ,  FISCHER JUERGEN ,  HEINEMANN ERIK ,  MARBACH-FISCHBACH IDA

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/31

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/3185 ,  H01L24/28 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01033 ,  H01L2924/01052

Abstract: The invention relates to the flip-chip mounting of semiconductor chips. In order to protect against mechanical stress or damage and to electrically insulate, a protective layer (7) is applied to the rear side of the semiconductor chip (2). This protective layer can also be provided on the flanks (8) of the semiconductor chip. The protective layer can be applied before starting the entire assembly process sequence or when the semiconductor is fixed upside down to a support (1).

Abstract translation: 在倒装芯片安装的半导体芯片：对于抗机械应力或损坏，保护和电绝缘性，在半导体芯片（2）的背面上的保护层（7）被施加。 该保护层也可以存在于半导体芯片的侧面（8）。 该保护层可以在整个装配过程链之前，或者只在所述半导体芯片的固定被施加在基板1上颠倒。

公开(公告)号：FR2883660B1

公开(公告)日：2013-06-21

申请号：FR0602199

申请日：2006-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PUSCHNER FRANK ,  HEINEMANN ERIK ,  JANKA STEPHAN

IPC: H01L23/31 ,  G06K19/077

公开(公告)号：AT291259T

公开(公告)日：2005-04-15

申请号：AT00965790

申请日：2000-08-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PUESCHNER FRANK ,  HEINEMANN ERIK ,  FISCHER JUERGEN

IPC: H01L23/28 ,  G06K19/077 ,  H01L21/56 ,  H01L21/60 ,  H01L23/12

公开(公告)号：DE50005936D1

公开(公告)日：2004-05-06

申请号：DE50005936

申请日：2000-12-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HEINEMANN ERIK ,  PUESCHNER FRANK ,  HOUDEAU DETLEF

IPC: G06K19/00 ,  G06K19/077

公开(公告)号：AT263398T

公开(公告)日：2004-04-15

申请号：AT00989819

申请日：2000-12-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HEINEMANN ERIK ,  PUESCHNER FRANK ,  HOUDEAU DETLEF

IPC: G06K19/00 ,  G06K19/077

公开(公告)号：DE10202727A1

公开(公告)日：2003-08-21

申请号：DE10202727

申请日：2002-01-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PUESCHNER FRANK ,  HEINEMANN ERIK

IPC: G06K19/077 ,  H01L23/50 ,  H01L23/12

公开(公告)号：AT233418T

公开(公告)日：2003-03-15

申请号：AT98943710

申请日：1998-07-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PUESCHNER FRANK ,  FISCHER JUERGEN ,  HEINEMANN ERIK

IPC: B42D15/10 ,  G06K19/077 ,  H01L23/12 ,  H01L23/28 ,  H01L23/50

Abstract: A method for producing a chip module includes punching a chip carrier to form a chip carrier fixing section and chip carrier contact sections spaced apart from the chip carrier fixing section by slots defining a given distance. The given distance is subsequently reduced to a dimension preventing a flow through of a sealing mass by a swaging operation carried out at least in a region close to the slots.