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公开(公告)号：DE102005005064A1
公开(公告)日：2006-08-10
申请号：DE102005005064
申请日：2005-02-03
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HOPPE WOLFGANG , DJORDJEVIC SRDJAN
Abstract: A semiconductor memory module, which is formed as an FBDIMM memory module, for example, has a planar design. In the 2Rx4 configuration, semiconductor components are arranged in two rows on a top side of a module board and semiconductor memory components are likewise arranged in two rows on an underside of the module board. In contrast to a "Stacked DRAM" design, the semiconductor components in accordance with the planar design contain only one memory chip. By using a parallel routing for a command address bus and an on-die termination bus, the address, clock, and control buses can be adapted in terms of load, so that different signal propagation times on the different buses are avoided to the greatest possible extent.
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公开(公告)号：DE10122701A1
公开(公告)日：2002-11-21
申请号：DE10122701
申请日：2001-05-10
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SCHOBER MARTIN , BENISEK MARTIN , HOPPE WOLFGANG
Abstract: A circuit module comprises a circuit board having a plurality of contact elements along a longitudinal edge thereof. The circuit board has arranged thereon a SDRAM memory component, the connections of this SDRAM memory component being each connected via resistance elements, which are implemented as individual resistors, to one of the contact elements through lines of limited length. The individual resistors are arranged in a line which extends parallel to the longitudinal direction of the circuit board.
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公开(公告)号：DE10021595B4
公开(公告)日：2006-01-19
申请号：DE10021595
申请日：2000-05-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor： MUFF SIMON , HOPPE WOLFGANG , GALL MARTIN , VASQUEZ BARBARA
IPC: G11C7/10 , H01L23/50 , H01L23/525 , H01L25/065
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Patent Agency Ranking
公开(公告)号：DE102006018874A1
公开(公告)日：2007-10-25
申请号：DE102006018874
申请日：2006-04-24
Applicant: INFINEON TECHNOLOGIES AG
Inventor： DJORDJEVIC SRDJAN , HOPPE WOLFGANG
Abstract: A circuit arrangement includes an arrangement of layers, wherein the arrangement of layers has a first surface and a second surface, at least one first and at least one second plated-through hole, at least one third plated-through hole, at least one first semiconductor component, and at least one second semiconductor component. A first layer from among the plurality of layers has a first conductive region and a second conductive region, which are coupled via a conductive connection. A second layer from among the plurality of layers has at least one first conductive region coupled to the first plated-through hole, and a second conductive region coupled to the second plated-through hole.
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公开(公告)号：DE102005005064B4
公开(公告)日：2006-12-21
申请号：DE102005005064
申请日：2005-02-03
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HOPPE WOLFGANG , DJORDJEVIC SRDJAN
Abstract: A semiconductor memory module, which is formed as an FBDIMM memory module, for example, has a planar design. In the 2Rx4 configuration, semiconductor components are arranged in two rows on a top side of a module board and semiconductor memory components are likewise arranged in two rows on an underside of the module board. In contrast to a "Stacked DRAM" design, the semiconductor components in accordance with the planar design contain only one memory chip. By using a parallel routing for a command address bus and an on-die termination bus, the address, clock, and control buses can be adapted in terms of load, so that different signal propagation times on the different buses are avoided to the greatest possible extent.
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公开(公告)号：DE102005005063A1
公开(公告)日：2006-08-17
申请号：DE102005005063
申请日：2005-02-03
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HOPPE WOLFGANG , DJORDJEVIC SRDJAN
IPC: H05K1/02
Abstract: A circuit board includes a first group of layers located close to a top side of the circuit board, and a second group of layers located close to an underside of the circuit board. Signals which are fed to input and output contact terminals on the top side of the circuit board are passed along at least one of the layers of the group. Signals which are fed to input and output contact terminals on the underside of the circuit board are passed along at least one of the layers of the second group. The contact-making holes for connecting the input and output contact terminals to the layers of the first and second groups are preferably formed as blind contact-making holes.
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公开(公告)号：DE10125911A1
公开(公告)日：2002-12-12
申请号：DE10125911
申请日：2001-05-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GALL MARTIN , HOPPE WOLFGANG , MUFF SIMON
Abstract: Device for enabling testing of proprietary or manufacturer memory chips with a standard system board. Device (100) for forming an interface between a first circuit board (102) for operation of a first memory module with a first clock signal, and a register for operating a command address bus of the first circuit board and a data bus of a first width and a second memory module (104) that is operated with a second clock signal and a buffer (110) for operating its command address bus. The device has the following characteristics: an arrangement (114) for matching first and second clock signals, an arrangement for matching buffer and register and an arrangement for matching the two data bus widths.
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公开(公告)号：DE10021595A1
公开(公告)日：2001-11-15
申请号：DE10021595
申请日：2000-05-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor： MUFF SIMON , HOPPE WOLFGANG , GALL MARTIN , VASQUEZ BARBARA
IPC: G11C7/10 , H01L23/50 , H01L23/525 , H01L25/065
Abstract: One configuration of an integrated semiconductor circuit can be selected from several possibilities. The supply and signal lines for all possibilities and one or more programming pins (1,2) lead out of the chip circuit housing (4) and the desired configuration is selected by means of a corresponding programming signal to the pins.
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