3.
    发明专利
    未知

    公开(公告)号:DE102004009173A1

    公开(公告)日:2005-09-15

    申请号:DE102004009173

    申请日:2004-02-25

    Abstract: In order to compensate for the shortening of line ends ( 30 ) in a circuit design of an integrated circuit, in a first step, hammerheads or serifs ( 50 ) are attached to the line ends ( 30 ) by means of rule-based OPC corrections. The line ends modified in this way are revised further by downstream application of a simulation-based OPC correction before mask or direct wafer writer data are calculated. As a result of the formation of the pattern revised by the simulation-based correction on the wafer, there actually arises in an approximate manner owing to the proximity effects the layout created by the rule-based correction with the supplemented line ends ( 30 ) on the wafer.

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