1.
    发明专利
    未知

    公开(公告)号:DE10143723B4

    公开(公告)日:2006-09-28

    申请号:DE10143723

    申请日:2001-08-31

    Abstract: A method of producing a layout for a mask for use in semiconductor production includes a two-stage, iterative optimization of the position of scatter bars in relation to main structures being carried out. In a first stage, following first production of scatter bars and carrying out an OPC, scatter bars are again generated based on the corrected main structures. A renewed OPC is then carried out, followed by the renewed formation of scatter bars. This is repeated until the layout has been optimized sufficiently. Then, in the second stage, defocused exposure of the layout is simulated and, if required, further adaptation of the scatter bars is carried out. The first and second iterative stages can also be employed independently of each other. The common factor in the iterations is that the scatter bar positions are varied with each iteration and is therefore optimized.

    5.
    发明专利
    未知

    公开(公告)号:DE102004009173A1

    公开(公告)日:2005-09-15

    申请号:DE102004009173

    申请日:2004-02-25

    Abstract: In order to compensate for the shortening of line ends ( 30 ) in a circuit design of an integrated circuit, in a first step, hammerheads or serifs ( 50 ) are attached to the line ends ( 30 ) by means of rule-based OPC corrections. The line ends modified in this way are revised further by downstream application of a simulation-based OPC correction before mask or direct wafer writer data are calculated. As a result of the formation of the pattern revised by the simulation-based correction on the wafer, there actually arises in an approximate manner owing to the proximity effects the layout created by the rule-based correction with the supplemented line ends ( 30 ) on the wafer.

    8.
    发明专利
    未知

    公开(公告)号:DE10356693A1

    公开(公告)日:2005-07-14

    申请号:DE10356693

    申请日:2003-11-27

    Abstract: A method for producing for a mask a mask layout which avoids aberrations in which a provisional auxiliary mask layout produced, in particular in accordance with a prescribed electrical circuit diagram is converted into the mask layout with the aid of an OPC method. At least two different OPC variants are used in the course of the OPC method by subdividing the original auxiliary mask layout into at least two layout areas and processing each of the layout areas in accordance with one of the at least two OPC variants.

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