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1.发明申请
公开(公告)号：WO0116997A3
公开(公告)日：2001-08-30
申请号：PCT/EP0008517
申请日：2000-08-31
Applicant: INFINEON TECHNOLOGIES AG , MEYER DIRK , LUDWIG BURKHARD , JUNGMANN ANGELIKA
Inventor： MEYER DIRK , LUDWIG BURKHARD , JUNGMANN ANGELIKA
IPC: G06F17/50
CPC classification number: G06F17/5068
Abstract: Data pertaining to a layout is described in a hierarchical form by cells and cell instances and is located in a first grid structure. Data for the mask is generated in a second grid structure. For each cell instance, the context is determined in the second grid structure. Cell variants are determined for cell instances with different contexts by rounding and scaling. Said cell variants contain the data for the mask in the second grid structure whereby rounding and scaling are context-dependent.
Abstract translation: 的布局的数据以分层的形式由细胞和Zellinstanziierungen并且位于第一栅格如前所述。 在第二栅格要产生所述掩模的数据。 给每个在所述第二网格的上下文的是用于确定Zellinstanziierungen。 对于具有不同上下文中，细胞变型中，通过舍入和缩放确定，其中包含在所述第二光栅掩模中的数据，其中所述舍入和缩放执行上下文敏感的Zellinstanziierungen。
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公开(公告)号：DE10224417B4
公开(公告)日：2007-08-02
申请号：DE10224417
申请日：2002-05-29
Applicant: INFINEON TECHNOLOGIES AG
Inventor： MEYER DIRK , ROESSLER THOMAS
Abstract: A method for classifying errors in the layout of a semiconductor circuit includes examining the layout of the semiconductor circuit for infringement of predetermined design rules in order to establish errors. For each error, the error is marked in the layout, and information about the error and the layout of the semiconductor circuit in an area surrounding the error is extracted. The extracted information is compared with prestored information within a multiplicity of classes, and the error is assigned to the respective class on the basis of the compared information.
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公开(公告)号：DE10224417A1
公开(公告)日：2003-12-24
申请号：DE10224417
申请日：2002-05-29
Applicant: INFINEON TECHNOLOGIES AG
Inventor： MEYER DIRK
Abstract: A method for classifying errors in the layout of a semiconductor circuit includes examining the layout of the semiconductor circuit for infringement of predetermined design rules in order to establish errors. For each error, the error is marked in the layout, and information about the error and the layout of the semiconductor circuit in an area surrounding the error is extracted. The extracted information is compared with prestored information within a multiplicity of classes, and the error is assigned to the respective class on the basis of the compared information.
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Patent Agency Ranking
公开(公告)号：DE10017767A1
公开(公告)日：2001-10-18
申请号：DE10017767
申请日：2000-04-10
Applicant: INFINEON TECHNOLOGIES AG
Inventor： FISCHER WERNER , LUDWIG BURKHARD , MEYER DIRK , THIELE JOERG
IPC: G03F1/00 , G06F17/50 , H01L21/312
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公开(公告)号：DE102005005591B3
公开(公告)日：2006-07-20
申请号：DE102005005591
申请日：2005-02-07
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SEMMLER ARMIN , MEYER DIRK , KOEHLE RODERICK , NOELSCHER CHRISTOPH , HEISMEIER MICHAEL , THIELE JOERG , LUDWIG BURKHARD
Abstract: The method involves dividing a pattern of a circuit design iteratively, into corresponding base patterns, to classify the parts of the pattern into the structural components which complies with the base patterns. Further base patterns are provided for the parts which are not classified. The geometries of the structural components are optimized and the optimized base patterns are inserted into the circuit design. An independent claim is also included for a use of a structural component geometry optimizing method for the production of a photomask.
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公开(公告)号：DE102004009173A1
公开(公告)日：2005-09-15
申请号：DE102004009173
申请日：2004-02-25
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HENKEL THOMAS , KECK MARTIN , THIELE JOERG , MEYER DIRK
Abstract: In order to compensate for the shortening of line ends ( 30 ) in a circuit design of an integrated circuit, in a first step, hammerheads or serifs ( 50 ) are attached to the line ends ( 30 ) by means of rule-based OPC corrections. The line ends modified in this way are revised further by downstream application of a simulation-based OPC correction before mask or direct wafer writer data are calculated. As a result of the formation of the pattern revised by the simulation-based correction on the wafer, there actually arises in an approximate manner owing to the proximity effects the layout created by the rule-based correction with the supplemented line ends ( 30 ) on the wafer.
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公开(公告)号：DE102004037297A1
公开(公告)日：2006-03-23
申请号：DE102004037297
申请日：2004-07-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor： MEYER DIRK , MUELLER UWE
IPC: H01L21/768 , G06F17/50 , H01L21/822 , H01L29/66
Abstract: A method for correcting layout errors of a layout, for example layout errors of a layout of an electronic circuit, is disclosed. In order to be able to correct such layout errors with the least possible complexity, the layout is examined for the presence of layout errors with the aid of predetermined design rules, identical layout errors are combined in a respective error class, and all layout errors of an error class that are still present are automatically corrected without further checking in an identical manner as soon as the correction of a layout error of the respective error class that is used as an error representative has been performed.
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公开(公告)号：DE19941400A1
公开(公告)日：2001-03-08
申请号：DE19941400
申请日：1999-08-31
Applicant: INFINEON TECHNOLOGIES AG
Inventor： MEYER DIRK , LUDWIG BURKHARD , JUNGMANN ANGELIKA
Abstract: Data pertaining to a layout is described in a hierarchical form by cells and cell instances and is located in a first grid structure. Data for the mask is generated in a second grid structure. For each cell instance, the context is determined in the second grid structure. Cell variants are determined for cell instances with different contexts by rounding and scaling. Said cell variants contain the data for the mask in the second grid structure whereby rounding and scaling are context-dependent.
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