Capacitance evaluation circuit e.g. for on-chip capacitance

    公开(公告)号:DE10010946A1

    公开(公告)日:2001-09-27

    申请号:DE10010946

    申请日:2000-03-06

    Abstract: The capacitance evaluation circuit has a test path (2) connected to one electrode of the capacitance (Cchar) to be evaluated, for application of 2 different potentials (V1,V2), the other electrode of the capacitance coupled to a second test (3) path with 2 parallel measuring paths connected to a common potential (V0), one of which contains a capacitance measuring instrument (1). A pair of potential sources may be coupled to the first test path via respective switch elements (SW1,SW2), with 2 further switch elements (SW3,SW4) for coupling one or other measuring path to the second electrode.

    Matrix capacitance evaluation circuit

    公开(公告)号:DE10010888A1

    公开(公告)日:2001-09-27

    申请号:DE10010888

    申请日:2000-03-06

    Abstract: The capacitance evaluation circuit has a test path (2) coupled to one electrode of each capacitance (Cchar) to be measured, for providing 2 different potentials (V1,V2) and a measuring path (3) coupled to the other electrode of the capacitance, having 2 parallel arms coupled to a common potential (V0), one of which contains a measuring instrument for evaluation of the capacitance. A control device allows each individual capacitance to be measured to be coupled to the 2 different potentials, using integrated switching transistors (T5,T6,T7,T8), using signals provided by an address decoder (10,11).

    4.
    发明专利
    未知

    公开(公告)号:DE50106894D1

    公开(公告)日:2005-09-01

    申请号:DE50106894

    申请日:2001-03-06

    Abstract: An apparatus and method for testing a plurality of electrical components that are coupled to one another. Further, an electrical selection unit, coupled to the electrical components to be tested, is provided for selecting at least one electrical component to be tested. A parasitic voltage drop in the testing circuit can be at least partially compensated using a control element coupled to the electrical components to be tested. The invention makes it possible, for testing of electrical components on a wafer over a large distance, i.e., several millimeters, to permit automated compensation of interference influences which occur as a result of the lines coupling or connecting the components to be tested.

    5.
    发明专利
    未知

    公开(公告)号:DE10010888B4

    公开(公告)日:2004-02-12

    申请号:DE10010888

    申请日:2000-03-06

    Abstract: A circuit configuration for assessing capacitances in a matrix, which has a number of rows with at least one capacitance in at least one dimension, includes a test arm connected to first electrodes of each of the capacitances to be assessed and by which two different potentials can be applied to the first electrodes, a measurement arm connected to second electrodes of each of the capacitances to be assessed and that has a first measurement path and a second measurement path connected to a common potential. The first measurement path has an instrument for assessing the capacitances and the first and second measurement paths can be connected to the second electrodes. The circuit configuration has a drive device that connects each of the capacitances to be assessed individually to the two different potentials.

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