公开(公告)号：DE59608187D1

公开(公告)日：2001-12-20

申请号：DE59608187

申请日：1996-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VON BASSE PAUL-WERNER ,  THEWES DR ,  SCHMITT-LANDSIEDEL DR ,  BOLLU DR

IPC: G11C11/412 ,  G11C7/12 ,  G11C17/12

Abstract: The matrix includes memory cells (1), each memory cell is provided with a MOSFET (10), and arranged in rows (2) and columns (3). The matrix columns lie between two adjacent bit lines (4) and selection lines (5) extend along each row. The selection lines are also connected to the gate of each memory cell transistor along respective line. An auxiliary MOSFET (20) is connected via its source and drain terminals to the adjacent bit lines, or to one bit line and a given potential. The gate electrode of this MOSFET coupled to a common bias line (6), allowing the bit lines to be selectively brought to a given potential.

公开(公告)号：DE59610239D1

公开(公告)日：2003-04-24

申请号：DE59610239

申请日：1996-11-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BASSE VON ,  THEWES DR ,  SCHMITT-LANDSIEDEL DR ,  BOLLU DR

IPC: G11C8/10 ,  G11C16/04 ,  G11C17/12

Abstract: The matrix memory has memory transistors (1) arranged in a row and column configuration, addressed via word lines (WL) and bit lines (BL) and control transistors (2) addressed via control lines (ST). Pref. the control transistors are arranged to act as a binary decoder with the same number of outputs as the number of pairs of bit lines for which memory transistors are provided, with a respective control line for each control transistor.

公开(公告)号：DE59813173D1

公开(公告)日：2005-12-15

申请号：DE59813173

申请日：1998-08-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHMITT-LANDSIEDEL DR ,  THEWES ROLAND ,  KOLLMER UTE ,  BOLLU DR ,  VON BASSE PAUL-WERNER ,  LUCK ANDREAS

IPC: G11C19/28 ,  G11C7/10 ,  G11C8/04 ,  G11C7/00

Abstract: The pointer circuit has a number of outputs (..,An-1, An,An+1,...), each individually associated with a static memory (1). There is a pair of complementary memory terminals at which different logic conditions ("1","0") are provided. One of the complementary memory terminals of each memory is coupled selectively to the memory output, with control of the memory via a clock signal.

公开(公告)号：DE59609221D1

公开(公告)日：2002-06-27

申请号：DE59609221

申请日：1996-03-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VON BASSE PAUL-WERNER ,  BOLLU DR ,  THEWES ROLAND ,  SCHMITT-LANDSIEDEL DR

IPC: G11C8/04 ,  G06F11/00 ,  G06F11/10 ,  G06F11/20 ,  G11C29/00 ,  G11C29/42

Abstract: The memory has a memory matrix (SM), with the memory cells (11,...ZS) coupled to row and column lines (ZL,SL). They are respectively associated with row and column selection devices (ZPTR ; SPTR,SCH), which are each indexed by a given step in response to each clock signal (CLK). The selection devices are formed so that when a new row is selected, only a limited number of columns can be selected and/or when a new column is selected only a limited number of rows can be selected. Pref. each selection device uses a number of shift registers connected in a ring.