公开(公告)号：DE59702679D1

公开(公告)日：2001-01-04

申请号：DE59702679

申请日：1997-07-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THEWES ROLAND ,  WEBER WERNER ,  LUCK ANDREAS ,  WOHLRAB ERDMUTE ,  SCHMITT-LANDSIEDEL DORIS

IPC: G06G7/60 ,  H03F1/22 ,  H03F3/16 ,  H03G1/00

Abstract: Amplifier circuits having at least one neuron MOS transistor in which a coupling gate is connected to an amplifier output and at least one further coupling gate is connected with a respective amplifier input are provided. The amplifier circuit exhibits a linear transmission behavior even in large-signal operation and can be constructed using relatively few components. Furthermore, the gain is easy to set.

公开(公告)号：DE59811228D1

公开(公告)日：2004-05-27

申请号：DE59811228

申请日：1998-09-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JUNG STEFAN ,  THEWES DR ,  WEBER DR ,  LUCK ANDREAS

IPC: G11C15/04

Abstract: The associative memory has a matrix of memory cells (Z) each having a standard PMOS transistor (T1) and a PMOS transistor (T2) having a floating gate (FG), connected in series between a supply voltage (Vdd) and an output vector bit signal terminal (Yj). An input vector bit signal terminal (Xk) is coupled to the gate of the first transistor and a learning signal terminal is coupled to the gate of the second transistor.

公开(公告)号：DE59813173D1

公开(公告)日：2005-12-15

申请号：DE59813173

申请日：1998-08-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHMITT-LANDSIEDEL DR ,  THEWES ROLAND ,  KOLLMER UTE ,  BOLLU DR ,  VON BASSE PAUL-WERNER ,  LUCK ANDREAS

IPC: G11C19/28 ,  G11C7/10 ,  G11C8/04 ,  G11C7/00

Abstract: The pointer circuit has a number of outputs (..,An-1, An,An+1,...), each individually associated with a static memory (1). There is a pair of complementary memory terminals at which different logic conditions ("1","0") are provided. One of the complementary memory terminals of each memory is coupled selectively to the memory output, with control of the memory via a clock signal.

公开(公告)号：DE59712268D1

公开(公告)日：2005-05-19

申请号：DE59712268

申请日：1997-09-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUCK ANDREAS ,  THEWES DR ,  WEBER DR

IPC: G06G7/60 ,  G06F7/52 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H03K19/20

Abstract: The circuit comprises a first and a second circuit part (CZ, SZ) which include an evaluation circuit (M1, M2, M3, M4, M7; M1', M2', M3', M4', M7') and elements (M5, M5', M6, M6') for an addition of weighted input sizes, respectively. A partial sum is formed in the first circuit part (CZ), and the partial sum is supplied to at least one of the adding elements of the second circuit part. The partial sum signal controls the channels of at least two neuron MOS transistors (M6, M6') in at least two circuit parts simultaneously over a common polysilicon area.