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    Semiconductor emitter element used in semiconductor diode lasers comprises semiconductor layer systems with electrically conducting layers, and a control element for applying voltage pulses between the electrically conducting layers
    3.
    发明专利
    Semiconductor emitter element used in semiconductor diode lasers comprises semiconductor layer systems with electrically conducting layers, and a control element for applying voltage pulses between the electrically conducting layers 未知

    公开(公告)号：DE10122072A1

    公开(公告)日：2002-11-21

    申请号：DE10122072

    申请日：2001-05-07

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LUYKEN JOHANNES R ,  STREIBL MARTIN ,  LORKE AXEL ,  KOTTHAUS JOERG

    IPC: H01L29/12 ,  H01L33/06 ,  H01S1/00 ,  H01S5/062 ,  H01S5/34 ,  H01S5/343

    Abstract: Semiconductor emitter element comprises a first semiconductor layer system having a first semiconductor layer (103) and a second semiconductor layer; a second semiconductor layer system having a third semiconductor layer (106); and a control element (108) for applying voltage pulses between the electrically conducting layers. Semiconductor emitter element comprises a first semiconductor layer system having a first semiconductor layer (103) of a first material grown on a first electrically conducting layer and a second semiconductor layer of a second material grown on the first semiconductor layer to form quantum dots (104) in the second semiconductor layer; a second semiconductor layer system having a third semiconductor layer (106) of a third material grown on the first semiconductor layer system with a second electrically conducting layer grown on the third layer; and a control element (108) for applying voltage pulses between the electrically conducting layers. The Fermi level of the first electrically conducting layer agrees with an excited energy level of the quantum dots to produce an electron tunnel through the first semiconductor layer and to prevent a tunnel of electrons through the third semiconductor layer. Independent claims are also included for the following: (a) a process for the production of the semiconductor emitter element; and (b) a process for operating the semiconductor emitter element. Preferred Features: The first material is of formula (I): (where n = 0-1) and the second material is indium arsenide (InAs) or gallium antimonide (GaSb). The third semiconductor layer is aluminum/gallium arsenide (Al/GaAs) super lattice.

    4.
    发明专利
    未知

    公开(公告)号：DE102004033148A1

    公开(公告)日：2006-02-09

    申请号：DE102004033148

    申请日：2004-07-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ILICALI GUERKAN ,  LUYKEN JOHANNES R ,  ROESNER WOLFGANG

    IPC: H01L21/336 ,  H01L29/78

    Abstract: A process for producing a layer arrangement, which layer arrangement allows a dual gate field-effect transistor to be formed. In this process, a porous silicon layer is formed as sacrificial layer on an auxiliary substrate. A first semiconductor layer is formed on the sacrificial layer, and a first electrically insulating layer is formed on the first semiconductor layer. An electrically conductive layer is formed on the first electrically insulating layer, which electrically conductive layer is laterally patterned. The first electrically insulating layer, the sacrificial layer and the first semiconductor layer are jointly laterally patterned using the laterally patterned electrically conductive layer as a mask. Furthermore, a semiconductor structure is formed adjacent to side walls of the patterned sacrificial layer and of the patterned first semiconductor layer. A substrate is secured over the patterned electrically conductive layer, and material of the auxiliary substrate is removed, so that the sacrificial layer is uncovered. Furthermore, the sacrificial layer is selectively removed, so as to form a trench, and a second electrically insulating layer is formed in the trench, then an electrically conductive structure is formed on this second electrically insulating layer.

    5.
    发明专利
    未知

    公开(公告)号：DE102004033147A1

    公开(公告)日：2006-02-09

    申请号：DE102004033147

    申请日：2004-07-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ILICALI GUERKAN ,  LUYKEN JOHANNES R ,  ROESNER WOLFGANG

    IPC: H01L21/336 ,  H01L29/78

    Abstract: A method for fabricating a double-gate transistor including defining an active area on an SOI substrate, forming a first gate region on the SOI substrate, forming source/drain regions made of silicon-germanium in the active area, forming a channel region from the silicon layer of the SOI substrate, forming a layer having a planar surface above the SOI substrate, the source/drain regions, and the first gate region, bonding a second wafer to the planar surface, and forming a second gate region opposite the first gate region.

    Circuit element, useful as memory, comprises a monomolecular layer of redox-active bis-pyridinium molecules situated between conductive layers
    7.
    发明专利
    Circuit element, useful as memory, comprises a monomolecular layer of redox-active bis-pyridinium molecules situated between conductive layers 未知

    公开(公告)号：DE10227850A1

    公开(公告)日：2004-01-15

    申请号：DE10227850

    申请日：2002-06-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LUYKEN JOHANNES R ,  SEITZ MARKUS ,  PREECE JON ,  WEBER WERNER ,  SCHMID GUENTER

    IPC: C07D213/22 ,  G11C13/02 ,  H01L27/28 ,  H01L51/30 ,  H01L51/20 ,  H01L51/40 ,  H01L51/00 ,  G11C11/21 ,  C07D213/00

    Abstract: A circuit element comprises a monomolecular layer of redox-active bis-pyridinium molecules situated between the first and second conductive layers, whereby the bis-pyridinium molecules of the monomolecular layer are immobilized on the electrically conductive layer as at least one discrete region. A circuit element (I) comprises a first layer of an electrically insulating substrate material with a first electrically conductive material comprising at least one discrete region that is embedded into or applied onto the substrate; a second layer with a second electrically conductive material and a monomolecular layer of redox-active bis-pyridinium molecules situated between the first and second layers, whereby the bis-pyridinium molecules of the monomolecular layer are immobilized on the electrically conductive layer as at least one discrete region and are in electrical contact with the second electrical material of the second layer and electrically inert molecules are immobilized on the first layer to form a matrix that surrounds at least one discrete region of the monomolecular layer of bispyridinium molecules. Independent claims are included for: (1) a process for the production of a circuit element (I) by application and/or embedding of a first electrically conductive material to at least one discrete position on/in the substrate material; immobilization of a monomolecular layer of redox-active bispyridinium molecules onto at least one discrete region of the first electrically conductive material; immobilization of electrically inert molecules onto the first layer of electrically insulating material that surround at least one region with the monomolecular layer of bis-pyridinium molecules; application of a second layer with a second electrically conductive material onto the layer of the electrically inert molecules and the bis-pyridinium molecules, whereby the bispyridinium molecules of the monomolecular layer are in contact with the second electrically material of the second layer; (2) bispyridinium compounds of formula (1) with the exclusion of N,N'-dimethyl-4,6,9,10-tetrahydro-2,7-diazapyreniumdiiodide; 1,1',2,2'-tetramethyl-4,4'-bispyridinium; 1,1',2-trimethyl-4,4'-bispyridinium; N,N'-dimethyl-2,7-diazapyrenium; N-methyl-N'-(p-toloyl)-2,7-diazapyrenium, 1,1'-dimethyl-2-phenyl-6-(p-toloyl)-4,4'-bispyridium diperchlorate; 1,1'-dimethyl-2-phenyl-4,4'-bispyridium diperchlorate; 6-(phenyl)-1,1',2-trimethyl-4,4'-bispyridium diperchlorate; 6-(phenyl)-1,1',2-trimethyl-4,4'-bispyridium diperchlorate or 1,1'-dimethyl-2-phenyl-6-(2,5-dichloro-3-thienyl)-4,4'-bispyridiumdiperchlorate. (1) Xa, XbS, N or O; Ra, Rbalkyl, aryl, alkylaryl, alkenyl, halogen, CN, OCN, COOH, COOR1>, CONHR1>, NO2, OH, OR1>, NH2, NHR1>, NR'R, SH or SR1>; R'R : alkyl, aryl, alkylaryl, alkenyl or alkinyl or Ra and Rb together form a bridge between the two aromatic ring systems comprising 1-3 atoms of C, S, N or O bonded by single, double or triple bonds and optionally substituted by Re; RcR a and Rb; Y : CH2, O, S, NH, NR1>, COO, CONH, CHCH, CC or aryl; Aa, ZbCH3, -CHCH2, SH, -SS-, SiCl3, Si(OR)3, SiR(OR')(OR), SiR(OR')2, Si(R'R)NH2, Si(R'2)NH2, COOH, SO3, PO3H or NH2; n, q : 0-12; j, k : 0-6; p., m : 0-12.

    9.
    发明专利
    未知

    公开(公告)号：DE102004033147B4

    公开(公告)日：2007-05-03

    申请号：DE102004033147

    申请日：2004-07-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ILICALI GUERKAN ,  LUYKEN JOHANNES R ,  ROESNER WOLFGANG

    IPC: H01L21/336 ,  H01L29/78

    Abstract: A method for fabricating a double-gate transistor including defining an active area on an SOI substrate, forming a first gate region on the SOI substrate, forming source/drain regions made of silicon-germanium in the active area, forming a channel region from the silicon layer of the SOI substrate, forming a layer having a planar surface above the SOI substrate, the source/drain regions, and the first gate region, bonding a second wafer to the planar surface, and forming a second gate region opposite the first gate region.

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