公开(公告)号：DE59913627D1

公开(公告)日：2006-08-10

申请号：DE59913627

申请日：1999-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  MAJDIC ANDREJ ,  MAZURE-ESPEJO CARLOS DR ,  HOENIGSCHMID HEINZ

IPC: G11C11/22

Abstract: An integrated memory device or store includes write-to memory cells (MC), a first differential read-amplifier (SA;SSA) with terminals connected to a data line pair (BLL;DL) allowing relevant information to be passed over the data lines as difference signals and temporarily stored at each write-access. A switch unit (SW) connects the data lines (BLL;DL) to the first read amplifier (SA;SSA) and reverse the terminals of the data lines to the read-amplifier depending on the switching state, where the latter changes at least once during a write-access so that the write-in information from the first amplifier (SA;SSA) is initially non-inverted and then inverted in the relevant memory cell (MC).

公开(公告)号：DE19844402C2

公开(公告)日：2002-11-14

申请号：DE19844402

申请日：1998-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  MAZURE-ESPEJO CARLOS ,  HOENIGSCHMID HEINZ ,  MAJDIC ANDREJ

IPC: G11C11/22 ,  G11C7/00

Abstract: An integrated memory device or store includes write-to memory cells (MC), a first differential read-amplifier (SA;SSA) with terminals connected to a data line pair (BLL;DL) allowing relevant information to be passed over the data lines as difference signals and temporarily stored at each write-access. A switch unit (SW) connects the data lines (BLL;DL) to the first read amplifier (SA;SSA) and reverse the terminals of the data lines to the read-amplifier depending on the switching state, where the latter changes at least once during a write-access so that the write-in information from the first amplifier (SA;SSA) is initially non-inverted and then inverted in the relevant memory cell (MC).

公开(公告)号：DE59902603D1

公开(公告)日：2002-10-10

申请号：DE59902603

申请日：1999-12-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  BRAUN GEORG ,  MAJDIC ANDREJ

IPC: G11C29/04 ,  G06F11/20 ,  G11C29/00

Abstract: An integrated memory has a normal bit line for transferring data from or to normal memory cells connected to it, and also a normal sense amplifier, which is connected via a line to the normal bit line and connected to a data line and amplifies data read from the normal memory cells. Furthermore, the memory has a redundant sense amplifier for replacing the normal sense amplifier in the redundancy situation. The redundant sense amplifier is likewise connected on the one hand to the line and on the other hand to the data line and, in the redundancy situation, serves for amplifying the data read from the normal memory cells. A method for repairing an integrated memory is also provided.