公开(公告)号：WO0065658A3

公开(公告)日：2001-03-29

申请号：PCT/DE0001303

申请日：2000-04-20

Applicant: INFINEON TECHNOLOGIES AG ,  WEINRICH VOLKER ,  SCHINDLER GUENTHER ,  MAZURE ESPEJO CARLOS

Inventor： WEINRICH VOLKER ,  SCHINDLER GUENTHER ,  MAZURE-ESPEJO CARLOS

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/06 ,  H01L27/105 ,  H01L21/8242

CPC classification number: H01L28/60 ,  H01L21/32136 ,  H01L27/0688

Abstract: The invention relates to a method of producing a high-epsilon dielectric/ferroelectric capacitor. According to the inventive method, a structural layer (10) with a central base-layer zone (11) and a trench (13) that is filled with Si and that laterally surrounds said layer is produced. A metal layer (14) is deposited on said layer and is siliconized above the Si-filled trench (13). When the siliconized metal layer section (18) is oxidized, it migrates into the trench (13), thereby forming a base electrode (19) above the base-layer zone (11).

Abstract translation: 在用于与中央基体层区（11）和有Si填充的沟槽围绕该横向制造高电介质基-ε-/铁电电容器结构化层（10）的方法（13）被产生。 此外，金属层（14）沉积和硅化在Si填充的沟槽（13）。 通过在沟槽（13），其特征在于，形成具有基极电极（19）的基本层区（11）氧化硅化金属层部分（18）迁移到这一点。

公开(公告)号：WO0001010A3

公开(公告)日：2002-10-03

申请号：PCT/DE9901770

申请日：1999-06-16

Applicant: INFINEON TECHNOLOGIES AG ,  ROEHR THOMAS ,  MAZURE-ESPEJO CARLOS ,  DEHM CHRISTINE

Inventor： ROEHR THOMAS ,  MAZURE-ESPEJO CARLOS ,  DEHM CHRISTINE

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/033

CPC classification number: H01L28/60 ,  H01L21/32139 ,  H01L2924/0002 ,  Y10S438/95 ,  H01L2924/00

Abstract: Disclosed is a method for producing semiconductor elements comprising a metal layer (10) arranged on a semiconductor substrate . The inventive method consists of the following steps: a silicon layer (30) is deposited on a metal layer (10); an etch mask is applied in order to structure the silicon layer (30); the silicon layer is selectively etched (30) using said etch mask (25); and the metal layer (10) is structured in an etching process using a selectively etched silicon layer (30) as a hard mask.

Abstract translation: 提出一种包括用于制造半导体器件的方法的步骤具有布置在半导体衬底金属层上（10）：所述金属层（10）上沉积硅层（30）; 施加的蚀刻掩模（25），用于图案化所述硅层（30）; 选择性地蚀刻使用蚀刻掩模（25）的硅层（30）; 以及使用该选择性地蚀刻硅层（30）作为硬掩模在蚀刻工艺图案化所述金属层（10）。

公开(公告)号：DE19919110C2

公开(公告)日：2002-06-27

申请号：DE19919110

申请日：1999-04-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEINRICH VOLKER ,  SCHINDLER GUENTHER ,  MAZURE-ESPEJO CARLOS

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/06 ,  H01L27/105 ,  H01L21/321 ,  H01L27/108

Abstract: In a method for fabricating a high-epsilon dielectric/ferroelectric capacitor, a patterning layer with a central base layer zone and a Si-filled trench laterally surrounding the latter is produced. Above that, a metal layer is deposited and is silicided above the Si-filled trench. Through oxidation of the silicided metal layer section the latter migrates into the trench and a base electrode is formed above the base layer zone.

公开(公告)号：DE59709642D1

公开(公告)日：2003-04-30

申请号：DE59709642

申请日：1997-09-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHINDLER GUENTHER ,  HARTNER WALTER ,  HINTERMAIER FRANK ,  MAZURE-ESPEJO CARLOS ,  BRUCHHAUS RAINER ,  HOENLEIN WOLFGANG ,  ENGELHARDT MANFRED

IPC: H01L27/10 ,  H01G4/00 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11502

Abstract: The integrated semiconductor memory configuration has a semiconductor body in which selection transistors and storage capacitors are integrated. The storage capacitors have a dielectric layer configured between two electrodes. At least the upper electrode is constructed in a layered manner with a platinum layer, that is seated on the dielectric layer, and a thicker, base metal layer lying above the platinum layer.

公开(公告)号：DE59807942D1

公开(公告)日：2003-05-22

申请号：DE59807942

申请日：1998-08-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HINTERMAIER FRANK ,  MAZURE-ESPEJO CARLOS

IPC: B05D7/24 ,  C01G29/00 ,  C01G35/00 ,  C23C16/40 ,  C23C18/12 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L41/24

Abstract: A bismuth-containing ceramic layer is produced using a bismuth precursor dissolved in a formic, acetic or propionic acid solvent. A ceramic layer is produced by (a) dissolving a bismuth precursor in a solvent of an organic acid of formula CnH2n+1COOH (n = 0, 1 or 2) and optionally water; (b) dissolving a further precursor in a further solvent and/or providing a further precursor in the liquid state; and (c) applying the precursors to a substrate and heating. Preferred Feature: The further solvent is the same organic acid or tetrahydrofuran. A strontium-bismuth tantalate layer is formed using a solution of Bi(OAc)3 and Sr(OAc)2 in acetic acid which is heated to above the melting point of a tantalum-containing precursor before mixing with the tantalum-containing precursor in the liquid state.

公开(公告)号：DE19844402C2

公开(公告)日：2002-11-14

申请号：DE19844402

申请日：1998-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  MAZURE-ESPEJO CARLOS ,  HOENIGSCHMID HEINZ ,  MAJDIC ANDREJ

IPC: G11C11/22 ,  G11C7/00

Abstract: An integrated memory device or store includes write-to memory cells (MC), a first differential read-amplifier (SA;SSA) with terminals connected to a data line pair (BLL;DL) allowing relevant information to be passed over the data lines as difference signals and temporarily stored at each write-access. A switch unit (SW) connects the data lines (BLL;DL) to the first read amplifier (SA;SSA) and reverse the terminals of the data lines to the read-amplifier depending on the switching state, where the latter changes at least once during a write-access so that the write-in information from the first amplifier (SA;SSA) is initially non-inverted and then inverted in the relevant memory cell (MC).

公开(公告)号：DE10025550A1

公开(公告)日：2001-11-29

申请号：DE10025550

申请日：2000-05-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEINRICH VOLKER ,  ENGELHARDT MANFRED ,  MAZURE-ESPEJO CARLOS

IPC: C23F4/00 ,  H01L21/3213 ,  H01L21/306

Abstract: Plasma etching at temperatures of above 100 deg C comprises applying a polyimide mask before the structure is etched. Preferred Features: The polyimide contains fluorine. The polyimide is formed on the wafer by crosslinking.

公开(公告)号：DE59711242D1

公开(公告)日：2004-02-26

申请号：DE59711242

申请日：1997-09-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HINTERMAIER FRANK ,  MAZURE-ESPEJO CARLOS

IPC: H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11517 ,  H01L29/788 ,  H01L29/792

Abstract: Process for producing an integrated semiconductor memory configuration, in particular one suited to the use of ferroelectric materials as storage dielectrics, in which a conductive connection between one electrode of a storage capacitor and a selection transistor is not produced until after the storage dielectric has been deposited; and a semiconductor memory configuration produced using the production process.

公开(公告)号：DE59709925D1

公开(公告)日：2003-05-28

申请号：DE59709925

申请日：1997-09-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTNER WALTER ,  SCHINDLER GUENTHER ,  MAZURE-ESPEJO CARLOS

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/108 ,  H01L29/92

Abstract: The invention relates to a semiconductor device for integrated circuits with a stack cell located in an insulating layer (2) having a plug (1) filled contact hole (8) with a capacitor with a lower electrode (5) turned towards the plug (1), a paraelectric or ferroelectric dielectric (6) and an upper electrode (7). A barrier layer (3) is located between the plug (1) and the lower electrode (5). Said layer is surrounded by a silicon nitride collar (4) preventing effective oxidation of barrier layer (3).

公开(公告)号：DE19819542C2

公开(公告)日：2002-10-24

申请号：DE19819542

申请日：1998-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MAZURE-ESPEJO CARLOS ,  ZELLER CHRISTOPH

IPC: G01J1/46 ,  G01D5/18 ,  G11C7/00 ,  G11C11/22 ,  G11C11/34 ,  G11C27/00 ,  G11C27/02 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/146 ,  H01L27/22 ,  H01L31/00

Abstract: A circuit includes a sensor delivering a charge, a capacitor non-volatilely storing the charge, and a read and reset circuit reading out the stored charge. The capacitor has further connection terminals connected to the read and reset circuit and in parallel with the sensor terminals, and a ferroelectric storage dielectric intermittently connected to the sensor. The sensor can be a photodiode, a phototransistor, a Hall sensor, or a thermoelement. A switch can be connected between one of the further terminals and one of the sensor terminals. Preferably, the switch is a transistor and a drive circuit drives it. The sensor and the capacitor are formed in a semiconductor body. During a storage procedure, time periods during which the switch is on are coordinated with the sensor and/or capacitor to keep an electrical field present between the further terminals below a maximum value at which the ferroelectric dielectric saturates.