公开(公告)号：JP2000243933A

公开(公告)日：2000-09-08

申请号：JP2000038344

申请日：2000-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  MANDEL SABINE ,  SCHNEIDER HELMUT

IPC: G11C8/00 ,  G11C5/02 ,  G11C5/14 ,  G11C7/18 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a decoder connecting device for a memory chip having a long bit line. SOLUTION: A dummy region 7 of a decoder 2 based on a bit line twist 8 is provided between a current supply line 3 and a decoder 2. In this case, bit lines BL form a line twist in a bit line twist region 8 in a memory cell field 1. Additional through holes 6 between two metallized surfaces are made in a zone of the decoder region 2 adjacent to the bit line twist region 8.

公开(公告)号：JP2000252440A

公开(公告)日：2000-09-14

申请号：JP2000046287

申请日：2000-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  MANDEL SABINE ,  SAVIGNAC DOMINIQUE DR ,  SCHNEIDER HELMUT

IPC: G11C7/18 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To avoid the affect of unevenness of the element at edge part on a crossover region or twist region of a bit line by providing with a bit line comprising no bit line twist part with a dummy contact communicated with another plane. SOLUTION: Bit lines BL1, BL2; BL5, BL6; BL9, BL10 comprise a bit line twist part. Bit lines BL3, BL4, BL7, and BL8 comprise no bit line twist part. In order to avoid a proximity effect caused by discontinuity or unevenness in a region near the word lines, even the bit lines BL3, BL4, BL7, and BL8 comprising no crossover or twist part are provided with dummy contacts 8-11. The dummy contacts 8-11 are connected to a word line plane from upward from a bit line plane, and terminate there. Thus, the effect of unevenness of word line is avoided.

公开(公告)号：DE50009385D1

公开(公告)日：2005-03-10

申请号：DE50009385

申请日：2000-02-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  MANDEL SABINE ,  SCHNEIDER HELMUT

IPC: G11C8/00 ,  G11C5/02 ,  G11C5/14 ,  G11C7/18 ,  H01L21/8242 ,  H01L27/108

Abstract: A decoder connection configuration for memory chips, in which, in a dummy region of a decoder, the dummy region being caused by a bit line twist, additional plated-through holes are provided between power supply lines and the decoder. By virtue of the bit line twist, the coupling capacitance is practically halved on account of the electrical symmetry.