公开(公告)号：DE102005057448A1

公开(公告)日：2006-07-27

申请号：DE102005057448

申请日：2005-12-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NIKUTTA WOLFGANG ,  NIRMAIER THOMAS

IPC: G01R31/28 ,  G01R31/3183

Abstract: An apparatus for generating an output signal having a higher frequency than a first signal received from a first external connector of a test equipment associated to a first channel and a second signal received on a second external connector of the test equipment associated to a second channel, having a first connector adapted to be connected to said first external connector, and adapted to receive the first signal, a second connector adapted to be connected to said second external connector, and adapted to receive the second signal, wherein the first and second signals are out of phase, an output to be connected to the device under test, and a passive circuit for combining the signals received at said first and second connector into the output signal and for providing said output signal to said output.

公开(公告)号：DE10159180A1

公开(公告)日：2003-06-12

申请号：DE10159180

申请日：2001-11-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NIKUTTA WOLFGANG

IPC: G11C7/10 ,  G11C7/22

Abstract: The memory has at least one memory module (105), which is provided as a memory module field (106) and has a synchronization connection (107) for a synchronization signal (111). Synchronization of the memory modules is provided, wherein data bursts stored in the memory modules and read out are combined to a data stream. An Independent claim is also provided for a storage and read out method for data streams.

公开(公告)号：DE10033441A1

公开(公告)日：2002-01-24

申请号：DE10033441

申请日：2000-07-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NIKUTTA WOLFGANG

IPC: G11C7/12 ,  G11C8/10 ,  G11C11/4094 ,  G11C11/407 ,  G11C29/00

Abstract: A dummy cell (10) generates a potential on a bit or reference line during a precharge interval lying between potential allocated to a read 0 and 1. The dummy cell is located outside the memory cell array (1-4) for all, or several cell arrays. Pref. tue common dummy cell comprises a capacity (COC) and a transistor (TR) to distribute the stored charge in the capacity to the activated reference bit line, on energising by the precharge signal (PRE). Local dummy cell transfer gates may be provided. An Independent claim is included for a dynamic semiconductor memory (SDRAM).

公开(公告)号：DE10016724A1

公开(公告)日：2001-10-11

申请号：DE10016724

申请日：2000-04-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NIKUTTA WOLFGANG

IPC: H03K5/00 ,  H03K5/135 ,  H03K5/26 ,  H03L7/081 ,  H04L7/00 ,  H03K5/125 ,  G01R31/3183

Abstract: The circuit arrangement includes a calibration circuit (2) which is connected with connections (11, 12) for at least two digital signals (E1, E2), and which comprises outputs (13, 14) for at least two digital output signals (Al, A2) which are respectively derived from one of the digital signals. A temporal control of a switching flank of one of the output signals results through the calibration circuit using a control value (R). A comparison circuit (3) is connected with the outputs (13, 14), and comprises a connection for a comparison signal (V) which indicates, that one of the output signals has a switching flank preceding that of the other output signal. The calibration circuit includes a memory circuit (4) for storing the control value, and a control input (21), over which the control value is adjustable using the condition of the comparison signal of the comparison circuit.

公开(公告)号：DE102004036786A1

公开(公告)日：2006-03-23

申请号：DE102004036786

申请日：2004-07-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZIELBAUER JUERGEN ,  NIKUTTA WOLFGANG

IPC: G11C29/00

Abstract: The chip (50) has a conditioning unit (M) including a set of possible conditions and whose current condition is expendably changed. A configuration device (74) configures a configurable integrated circuit arrangement depending upon the current condition of the conditioning unit. A selection device (66) enables selection of information, which depends on the current condition of the conditioning unit. An independent claim is also included for a procedure for verifying a configuration of the chip with a configurable integrated circuit arrangement.

公开(公告)号：DE59510495D1

公开(公告)日：2003-01-16

申请号：DE59510495

申请日：1995-04-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NIKUTTA WOLFGANG ,  RECZEK DR

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/06

Abstract: The circuit has a semiconductor substrate with a number of potential rails (P1-i) connected to a first supply potential (VSS-i) and a number of potential rails (P2-i) connected to a second supply potential (VCC-i), between which a number of circuit stages (Si) are connected. Each circuit stage has an input/output terminal (PAD-ij) coupled to it via an overvoltage protection circuit (ESD-i), with a discharge path (EP) for diverting the overvoltage, coupled to a collector potential rail (P-ESD) for all the protection circuits.

公开(公告)号：DE10140344A1

公开(公告)日：2003-03-06

申请号：DE10140344

申请日：2001-08-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER ANDRE ,  NIKUTTA WOLFGANG ,  BORCKE MATHIAS VON ,  KANDOLF HELMUT

IPC: H03K5/01 ,  H03K17/16 ,  H03K17/693 ,  H03K5/12 ,  H03K6/04

Abstract: The signal driver (100) has a first unit (102) for driving the signal (Vout) from first level in direction to a second level and a line of intermediate levels, contg. an intermediate level different from a reference level. The reference level lies between the first and second signal levels. A second unit (106) drives the signal in the direction of the second signal level from the last intermediate level of the line of intermediate levels. Independent claims are included for integrated circuit contg. the signal driver.

公开(公告)号：DE10116325A1

公开(公告)日：2002-10-17

申请号：DE10116325

申请日：2001-04-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NIKUTTA WOLFGANG

IPC: G11C7/06 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094

Abstract: The circuit has a number of memory cells activated by word lines arranged as columns and bit lines arranged as rows connected to read amplifiers. Activating a word line connects at least a first bit line of a memory cell to a read amplifier to read out a data item. A read amplifier actively places a second bit line adjacent to a first bit line at a defined potential while the first bit line is being read out. AN Independent claim is also included for the following: a method for reading out a data item from a memory cell.

公开(公告)号：DE10110625A1

公开(公告)日：2002-09-19

申请号：DE10110625

申请日：2001-03-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NIKUTTA WOLFGANG

IPC: G11C7/06 ,  G11C11/4091

Abstract: The read-out signal is read-out from a memory cell, compared with a reference value by a comparison circuit of the amplifier, valuated and transmitted in amplified mode.In a first step the two memory capacitors (1,2) are charged with a biassing potential temporarily. In a second step a read-out signal is read-out from a memory cell and fed to one of the two capacitors. In a third step the capacitor potential difference is determined, amplified, and in a fourth step the amplified signal is transmitted. Independent claims are included for a read-out amplifier circuit.

公开(公告)号：AT229230T

公开(公告)日：2002-12-15

申请号：AT95105212

申请日：1995-04-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NIKUTTA WOLFGANG ,  RECZEK WERNER DR

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/06

Abstract: The circuit has a semiconductor substrate with a number of potential rails (P1-i) connected to a first supply potential (VSS-i) and a number of potential rails (P2-i) connected to a second supply potential (VCC-i), between which a number of circuit stages (Si) are connected. Each circuit stage has an input/output terminal (PAD-ij) coupled to it via an overvoltage protection circuit (ESD-i), with a discharge path (EP) for diverting the overvoltage, coupled to a collector potential rail (P-ESD) for all the protection circuits.