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    Method of manufacturing conductor track array
    1.
    发明专利
    Method of manufacturing conductor track array 有权
    制造导线跟踪阵列的方法

    公开(公告)号：JP2011129939A

    公开(公告)日：2011-06-30

    申请号：JP2011009120

    申请日：2011-01-19

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アーゲー

    Inventor： GABRIC ZVONIMIR ,  PAMLER WERNER ,  SCHINDLER GUENTHER ,  STICH ANDREAS

    IPC: H01L23/522 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/768

    CPC classification number: H01L21/7682

    Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing an air gap between conductor tracks that decreases in coupling capacity and is improved in mechanical or electrical characteristics as compared with conventional examples. SOLUTION: A conductor track array includes bases 1 and 2, at least two conductor tracks 4, a cavity 6, and a resist layer 5 covering the conductor tracks 4 to close the cavity 6. A carrier track TB having a width B2 narrower than the width B1 of the conductor tracks 4 is formed to form the air gap for reducing coupling capacity and signal delay by self-alignment technique below the conductor tracks 4 along side faces thereof. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种制造传导轨道之间的空气间隙的方法，其与传统实例相比降低了耦合能力，并提高了机械或电气特性。 解决方案：导体轨道阵列包括基座1和2，至少两个导体轨道4，空腔6和覆盖导体轨道4以封闭空腔6的抗蚀剂层5.具有宽度B2的载体轨道TB 形成比导体轨道4的宽度B1窄的狭缝，以形成气隙，用于通过导电轨道4沿着其侧面的自对准技术降低耦合电容和信号延迟。 版权所有（C）2011，JPO＆INPIT

    Conductive track array and its manufacturing method
    2.
    发明专利
    Conductive track array and its manufacturing method 有权
    导电跟踪阵列及其制造方法

    公开(公告)号：JP2007088439A

    公开(公告)日：2007-04-05

    申请号：JP2006224010

    申请日：2006-08-21

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： GABRIC ZVONIMIR ,  PAMLER WERNER ,  SCHINDLER GUENTHER ,  STICH ANDREAS

    IPC: H01L21/768 ,  H01L23/522

    CPC classification number: H01L21/7682

    Abstract: PROBLEM TO BE SOLVED: To provide a conductive track array with reduced coupling capacity and improved mechanical and electrical properties, and its manufacturing method. SOLUTION: The conductive track array includes substrates 1 and 2, at least two conductive tracks 4, cavity 6, and a resist layer 5 that fills up the cavity 6 and covers the conductive track 4. An air gap to reduce the coupling capacity and signal delay by forming a carrier track TB with width of B2, which is smaller than the width B1 of the conductive track 4, is formed under the conductive track 4 along its side wall using a self-align technology. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供具有降低的耦合能力和改善的机械和电气性能的导电轨道阵列及其制造方法。 解决方案：导电轨道阵列包括衬底1和2，至少两个导电轨道4，空腔6以及填充空腔6并覆盖导电轨道4的抗蚀剂层5。 使用自对准技术，通过形成宽度小于导电轨道4的宽度B1的B2的载体轨道TB，沿着其侧壁形成在导电轨道4的下方的容量和信号延迟。 版权所有（C）2007，JPO＆INPIT

    BOARD ON WHICH AT LEAST TWO METAL STRUCTURES ARE ARRANGED AND ITS MANUFACTURING METHOD
    4.
    发明专利
    BOARD ON WHICH AT LEAST TWO METAL STRUCTURES ARE ARRANGED AND ITS MANUFACTURING METHOD 失效

    公开(公告)号：JP2001210715A

    公开(公告)日：2001-08-03

    申请号：JP2000363142

    申请日：2000-11-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHWARZL SIEGFRIED ,  PAMLER WERNER ,  GABRIC ZVONIMIR

    IPC: H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/522 ,  H05K1/02

    Abstract: PROBLEM TO BE SOLVED: To provide a board on which at least two metal structures that can be manufactured through a damascene process with small capacitance. SOLUTION: A first insulating layer is arranged on a board, and a second insulating layer formed of metal different form the material of the first insulating layer is formed on the first insulating layer. A cavity is provided inside the first insulating layer, covered with the second insulating layer, and demarcated with a part of the first insulating layer against the board. Metal structures are arranged separate from each other by a certain space, and the upper horizontal surfaces of the metal structures are flush with the upper horizontal surface of the second insulting layer. At least, the cavity is characteristically arranged between the two metal structures so as not to come into contact with the metal structures arranged on the board.

    METHOD FOR DEPOSITING A CONDUCTIVE MATERIAL ON A SUBSTRATE, AND SEMICONDUCTOR CONTACT DEVICE
    8.
    发明申请
    METHOD FOR DEPOSITING A CONDUCTIVE MATERIAL ON A SUBSTRATE, AND SEMICONDUCTOR CONTACT DEVICE 审中-公开
    处理对导电材料上的基板及半导体装置的触点断开

    公开(公告)号：WO2005033358A3

    公开(公告)日：2005-07-21

    申请号：PCT/EP2004010892

    申请日：2004-09-29

    Applicant: INFINEON TECHNOLOGIES AG ,  GUTSCHE MARTIN ,  KREUPL FRANZ ,  PAMLER WERNER ,  SEIDEL ROBERT

    Inventor： GUTSCHE MARTIN ,  KREUPL FRANZ ,  PAMLER WERNER ,  SEIDEL ROBERT

    IPC: C23C16/02 ,  C23C16/04 ,  C23C16/26 ,  C23C16/44 ,  C23C16/455 ,  H01L21/3205

    CPC classification number: C23C16/0209 ,  C23C16/045 ,  C23C16/26 ,  C23C16/45557

    Abstract: The invention relates to a method for depositing a carbon material (17) in or on a substrate (14). Said method comprises the following steps: the inside (10') of a processing chamber (10) is heated to a pre-determined temperature; the substrate (14) is introduced into the processing chamber (10); the air in the processing chamber (10) is evacuated until a pre-determined pressure or a lower pressure is reached; a gas (12) containing at least carbon is introduced until a second pre-determined pressure is reached, that is higher than the first pre-determined pressure; and the carbon material (17) is deposited on a surface or in a recess (15), from the gas (12) containing carbon. The invention also relates to a semiconductor contact device.

    Abstract translation: 本发明提供了用于在或基板（14）上沉积的碳材料（17），其包括以下步骤的方法：处理室（10）加热的内部空间（10“）到预定的温度; 放置在处理室中的基板（14）（10）; 抽空所述处理室（10）到第一预定压力或更低; 引入气体（12），其具有至少碳，​​直到达到第二预定压力，其比第一预定压力更高; 和沉积所述碳材料（17）上的表面上或在从含碳气体（12）的凹部（15）。 本发明还提供了一种半导体接触装置。

    HOLLOW STRUCTURE IN AN INTEGRATED CIRCUIT
    9.
    发明申请
    HOLLOW STRUCTURE IN AN INTEGRATED CIRCUIT 审中-公开
    中空结构在集成电路

    公开(公告)号：WO02095820A3

    公开(公告)日：2003-02-06

    申请号：PCT/DE0201699

    申请日：2002-05-10

    Applicant: INFINEON TECHNOLOGIES AG ,  PAMLER WERNER ,  ENGELHARDT MANFRED ,  GABRIC ZVONIMIR

    Inventor： PAMLER WERNER ,  ENGELHARDT MANFRED ,  GABRIC ZVONIMIR

    IPC: H01L21/768

    CPC classification number: H01L21/7682

    Abstract: The invention relates to a hollow structure (100) in an integrated circuit, comprising a substrate (101) having a surface (102), conductor tracks (103) which are adjacently arranged on said surface in such a way that they form intermediate spaces (104) thereinbetween, a first layer (105) consisting of a first insulation material which is arranged over each conductor track (103), and a second layer (106) covering the intermediate spaces (104), consisting of a second insulation material which is deposited only on the first insulation material.

    Abstract translation: 在集成电路中的空腔结构（100）包括具有基片表面（102）在其上的并置的导电迹线（103）与中间空间（104）布置成一个各导体轨道（103）的第一层上的基板（101）（ 覆盖105）的第一绝缘材料制成，并且由能够仅在所述第一绝缘材料上沉积第二绝缘材料的间隙（104）的第二层（106）。

    10.
    发明专利
    未知

    公开(公告)号：DE10207130B4

    公开(公告)日：2007-09-27

    申请号：DE10207130

    申请日：2002-02-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WEINRICH VOLKER ,  PAMLER WERNER ,  GABRIC ZVONIMIR

    IPC: H01L21/283 ,  H01L27/108 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115

    Abstract: A method for improving the adhesion between a noble metal layer and an insulation layer includes configuring a silicon layer between the noble metal layer and the insulation layer. The silicon layer is siliconized and oxidized by a thermal treatment in an oxidative environment, resulting in an oxidized silicide layer with high intermixing of the noble metal and the formed oxide. The relatively large inner surface achieved as a result improves the adhesion between the noble metal layer and the insulation layer.

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