公开(公告)号：JP2011129939A

公开(公告)日：2011-06-30

申请号：JP2011009120

申请日：2011-01-19

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アーゲー

Inventor： GABRIC ZVONIMIR ,  PAMLER WERNER ,  SCHINDLER GUENTHER ,  STICH ANDREAS

IPC: H01L23/522 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/768

CPC classification number: H01L21/7682

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing an air gap between conductor tracks that decreases in coupling capacity and is improved in mechanical or electrical characteristics as compared with conventional examples. SOLUTION: A conductor track array includes bases 1 and 2, at least two conductor tracks 4, a cavity 6, and a resist layer 5 covering the conductor tracks 4 to close the cavity 6. A carrier track TB having a width B2 narrower than the width B1 of the conductor tracks 4 is formed to form the air gap for reducing coupling capacity and signal delay by self-alignment technique below the conductor tracks 4 along side faces thereof. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种制造传导轨道之间的空气间隙的方法，其与传统实例相比降低了耦合能力，并提高了机械或电气特性。 解决方案：导体轨道阵列包括基座1和2，至少两个导体轨道4，空腔6和覆盖导体轨道4以封闭空腔6的抗蚀剂层5.具有宽度B2的载体轨道TB 形成比导体轨道4的宽度B1窄的狭缝，以形成气隙，用于通过导电轨道4沿着其侧面的自对准技术降低耦合电容和信号延迟。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2007088439A

公开(公告)日：2007-04-05

申请号：JP2006224010

申请日：2006-08-21

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： GABRIC ZVONIMIR ,  PAMLER WERNER ,  SCHINDLER GUENTHER ,  STICH ANDREAS

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/7682

Abstract: PROBLEM TO BE SOLVED: To provide a conductive track array with reduced coupling capacity and improved mechanical and electrical properties, and its manufacturing method. SOLUTION: The conductive track array includes substrates 1 and 2, at least two conductive tracks 4, cavity 6, and a resist layer 5 that fills up the cavity 6 and covers the conductive track 4. An air gap to reduce the coupling capacity and signal delay by forming a carrier track TB with width of B2, which is smaller than the width B1 of the conductive track 4, is formed under the conductive track 4 along its side wall using a self-align technology. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供具有降低的耦合能力和改善的机械和电气性能的导电轨道阵列及其制造方法。 解决方案：导电轨道阵列包括衬底1和2，至少两个导电轨道4，空腔6以及填充空腔6并覆盖导电轨道4的抗蚀剂层5。 使用自对准技术，通过形成宽度小于导电轨道4的宽度B1的B2的载体轨道TB，沿着其侧壁形成在导电轨道4的下方的容量和信号延迟。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2003258127A

公开(公告)日：2003-09-12

申请号：JP2003040423

申请日：2003-02-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GABRIC ZVONIMIR ,  PAMLER WERNER ,  WEINRICH VOLKER

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115

Abstract: PROBLEM TO BE SOLVED: To provide the manufacturing method of constituents improved in the adhesion of a noble metal layer to an insulation layer. SOLUTION: The method for improving adhesion between the noble metal layer (28) and the insulation layer (34) is proposed. In this method, a silicon layer is provided between the noble metal layer (28) and the insulation layer (34). The silicon layer is salicided and oxidized by applying heat treatment in an atmosphere where oxygen is present. In this case, an oxidized silicon layer (30'), effecting strong mixture of the noble metal and the formed oxide, is produced. Adhesion of the noble metal layer (28) to the insulation layer (34) is improved, based on a comparatively large internal surface acquired by this method. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2002076296A

公开(公告)日：2002-03-15

申请号：JP2001253003

申请日：2001-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHINDLER GUENTHER DR ,  GABRIC ZVONIMIR ,  HARTNER WALTER

IPC: H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method capable of etching a contact hole, after coating an effective hydrogen barrier using a simple method, and to provide a microelectronic constituent member. SOLUTION: A method for manufacturing the microelectronic constituent member comprises the steps of forming a memory capacitor (3) containing a first electrode (31), a second electrode (32) and a ferroelectric or paraelectric dielectric (33) between the electrodes (31, 32) on a substrate (1); first, forming a silicon oxide (41) in the case of forming a barrier (4) to form the barrier (4) for protecting against infiltration of hydrogen onto the capacitor (3); annealing at least a part of the capacitor (3) and the silicon oxide (41); and coating the barrier layer (42) for protecting against the infiltration of hydrogen on the annealed silicon oxide layer (41). The microelectronic constituent member manufactured by the method is provided.

公开(公告)号：JP2001210715A

公开(公告)日：2001-08-03

申请号：JP2000363142

申请日：2000-11-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHWARZL SIEGFRIED ,  PAMLER WERNER ,  GABRIC ZVONIMIR

IPC: H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/522 ,  H05K1/02

Abstract: PROBLEM TO BE SOLVED: To provide a board on which at least two metal structures that can be manufactured through a damascene process with small capacitance. SOLUTION: A first insulating layer is arranged on a board, and a second insulating layer formed of metal different form the material of the first insulating layer is formed on the first insulating layer. A cavity is provided inside the first insulating layer, covered with the second insulating layer, and demarcated with a part of the first insulating layer against the board. Metal structures are arranged separate from each other by a certain space, and the upper horizontal surfaces of the metal structures are flush with the upper horizontal surface of the second insulting layer. At least, the cavity is characteristically arranged between the two metal structures so as not to come into contact with the metal structures arranged on the board.

公开(公告)号：WO02071482A8

公开(公告)日：2003-08-28

申请号：PCT/DE0200554

申请日：2002-02-15

Applicant: INFINEON TECHNOLOGIES AG ,  PAMLER WERNER ,  SCHWARZL SIEGFRIED ,  GABRIC ZVONIMIR

Inventor： PAMLER WERNER ,  SCHWARZL SIEGFRIED ,  GABRIC ZVONIMIR

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a hollow structure (100) in an integrated circuit, comprising a first layer (101), a first layer surface (103) and webs (104) disposed thereon one beside the other, said webs including interstices (401), and a second layer (105) and a third layer (106) disposed thereon. The hollow structure further comprises a fourth layer (107) that closes some of the interstices (401), said fourth layer being disposed on the third layer (106) and having a second layer surface (108), the interstices (401) not being closed by the fourth layer (107) being filled with an electrically conducting material.

Abstract translation: 在集成电路中的空腔结构（100）具有第一层（101），第一层表面（103）并在此并排腹板（104），其包括间隙（401）和第二层（105）和随后的 第三层（106），具有一些间隙（401）最终第四布置在第三层（106）和第二层表面（108）在层（107），并且其中所述第四层的装置（107 ）未完成中间空间（401）填充有导电材料。

公开(公告)号：WO2005071739A3

公开(公告)日：2006-03-02

申请号：PCT/DE2005000088

申请日：2005-01-22

Applicant: INFINEON TECHNOLOGIES AG ,  GABRIC ZVONIMIR ,  PAMLER WERNER ,  SCHINDLER GUENTHER

Inventor： GABRIC ZVONIMIR ,  PAMLER WERNER ,  SCHINDLER GUENTHER

IPC: C23C16/30 ,  H01L21/314 ,  H01L21/764 ,  H01L21/768 ,  C23C16/40 ,  H01L21/76

CPC classification number: H01L21/764 ,  C23C16/308 ,  H01L21/3145 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: The invention relates to a plasma-excited chemical vapor deposition method for forming a silicon/oxygen/nitrogen-containing material. The invention provides that during the supply of silicon material and oxygen material, nitrogen material is supplied while using an organic silicon precursor material.

Abstract translation: 本发明涉及等离子体增强化学气相沉积工艺用于形成含有硅 - 氧 - 氮的材料，其中，所述含氮材料由硅材料和氧材料的供应过程中使用有机硅前体材料提供。

公开(公告)号：WO02091432A3

公开(公告)日：2003-05-01

申请号：PCT/EP0204422

申请日：2002-04-22

Applicant: INFINEON TECHNOLOGIES AG ,  HARTNER WALTER ,  GABRIC ZVONIMIR ,  KROENKE MATTHIAS ,  SCHINDLER GUENTHER

Inventor： HARTNER WALTER ,  GABRIC ZVONIMIR ,  KROENKE MATTHIAS ,  SCHINDLER GUENTHER

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L23/00 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L21/768

CPC classification number: H01L28/55 ,  H01L23/564 ,  H01L27/11502 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a microelectronic structure, which provides improved protection of a hydrogen-sensitive dielectric against hydrogen contamination. According to the invention, the hydrogen-sensitive dielectric (14) is covered at least by an intermediate oxide (18), whose material thickness is at least five times the thickness of the hydrogen-sensitive dielectric. The intermediate oxide (18) simultaneously acts as an intermetal dielectric and is metallized on its surface for this purpose. The intermediate oxide (18), which has a sufficient thickness, absorbs the hydrogen that may be released during the deposition of a hydrogen barrier layer (22, 26), thus protecting the hydrogen-sensitive dielectric (14).

Abstract translation: 建议用之前的氢污染氢敏感电介质的改进的保护微电子结构。 为了这个目的，提供了氢气敏感电介质（14），以至少覆盖中间氧化物（18），其厚度为氢敏电介质的厚度的至少五倍。 中间氧化物（18）同时用作金属间介电，并且因此携带在其上侧金属化。 的足够厚的中间氧化物（18）吸收可能在氢阻挡层（22，26）释放的氢的沉积和保护氢敏感电介质（14）。

公开(公告)号：WO02095820A3

公开(公告)日：2003-02-06

申请号：PCT/DE0201699

申请日：2002-05-10

Applicant: INFINEON TECHNOLOGIES AG ,  PAMLER WERNER ,  ENGELHARDT MANFRED ,  GABRIC ZVONIMIR

Inventor： PAMLER WERNER ,  ENGELHARDT MANFRED ,  GABRIC ZVONIMIR

IPC: H01L21/768

CPC classification number: H01L21/7682

Abstract: The invention relates to a hollow structure (100) in an integrated circuit, comprising a substrate (101) having a surface (102), conductor tracks (103) which are adjacently arranged on said surface in such a way that they form intermediate spaces (104) thereinbetween, a first layer (105) consisting of a first insulation material which is arranged over each conductor track (103), and a second layer (106) covering the intermediate spaces (104), consisting of a second insulation material which is deposited only on the first insulation material.

Abstract translation: 在集成电路中的空腔结构（100）包括具有基片表面（102）在其上的并置的导电迹线（103）与中间空间（104）布置成一个各导体轨道（103）的第一层上的基板（101）（ 覆盖105）的第一绝缘材料制成，并且由能够仅在所述第一绝缘材料上沉积第二绝缘材料的间隙（104）的第二层（106）。

公开(公告)号：WO02071482A2

公开(公告)日：2002-09-12

申请号：PCT/DE0200554

申请日：2002-02-15

Applicant: INFINEON TECHNOLOGIES AG ,  PAMLER WERNER ,  SCHWARZL SIEGFRIED ,  GABRIC ZVONIMIR

Inventor： PAMLER WERNER ,  SCHWARZL SIEGFRIED ,  GABRIC ZVONIMIR

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a hollow structure (100) in an integrated circuit, comprising a first layer (101), a first layer surface (103) and webs (104) disposed thereon one beside the other, said webs including interstices (401), and a second layer (105) and a third layer (106) disposed thereon. The hollow structure further comprises a fourth layer (107) that closes some of the interstices (401), said fourth layer being disposed on the third layer (106) and having a second layer surface (108), the interstices (401) not being closed by the fourth layer (107) being filled with an electrically conducting material.

Abstract translation: 在集成电路中的空腔结构（100）具有第一层（101），第一层表面（103）并在此并排腹板（104），其包括间隙（401）和第二层（105）和随后的 第三层（106），具有一些间隙（401）最终第四布置在第三层（106）和第二层表面（108）在层（107），并且其中所述第四层的装置（107 ）未完成中间空间（401）填充有导电材料。