公开(公告)号：JP2007096268A

公开(公告)日：2007-04-12

申请号：JP2006187619

申请日：2006-07-07

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： FUHRMANN DIRK ,  PERRY ROBERT ,  REHM NORBERT ,  UNG RATH ,  ZIELEMAN JAN

IPC: H01L21/66

CPC classification number: G01R31/31722 ,  G11C29/006 ,  G11C29/028 ,  G11C2029/0407 ,  G11C2029/2602 ,  G11C2029/4402 ,  G11C2029/5602

Abstract: PROBLEM TO BE SOLVED: To provide a method and system which can obtain a method and apparatus setting wafer chips with a single power on and off sequence, and further adjust a chip parameter during a wafer test without utilizing the sequence.
SOLUTION: The method comprises the steps of: assigning a specific identifier to a controllable chip resistor by a program of each wafer chip for test (step 52); storing a value of the parameter fixed by corresponding to each of them inside the chip resistor of the chip selected based on its identifier (step 54); and performing a test evaluating a setting of the parameter for each chip with a desired parameter set simultaneously (step 56).
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种方法和系统，其可以获得具有单个功率开启和关闭序列来设置晶片芯片的方法和装置，并且在晶片测试期间进一步调整芯片参数而不利用该序列。 该方法包括以下步骤：通过用于测试的每个晶片芯片的程序将特定标识符分配给可控芯片电阻器（步骤52）; 根据其标识符将所选择的芯片的片式电阻器中的每一个固定的参数的值存储在其中（步骤54）; 并且执行用同时设定的期望参数来评估每个芯片的参数的设置的测试（步骤56）。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：DE102006030360A1

公开(公告)日：2007-03-15

申请号：DE102006030360

申请日：2006-06-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FUHRMANN DIRK ,  PERRY ROBERT ,  REHM NORBERT ,  UNG RATH ,  ZIELEMAN JAN

IPC: H01L21/66 ,  G01R31/28 ,  G11C29/48

Abstract: A method and apparatus according to the present invention enable wafer chips to be configured with a single power on and off sequence and further enable a chip parameter to be adjusted during a wafer test without utilizing that sequence. In particular, each wafer chip under test is assigned a unique programmable identification. Once each chip has been assigned a corresponding identification, the chips may each be individually accessible by that identification to provide parameter values to chip registers to configure that chip. The configured chips may be subsequently tested in parallel to evaluate the parameter settings. In addition, the present invention enables chips to share data I/O pins or lines, thereby reducing the quantity of testing machine pins utilized for each chip and enabling a greater quantity of chips to be tested in a parallel fashion.

公开(公告)号：DE102005050394A1

公开(公告)日：2006-05-04

申请号：DE102005050394

申请日：2005-10-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PERRY ROBERT ,  REHM NORBERT ,  ZIELEMAN JAN

IPC: G11C29/12

Abstract: A memory device and methods to exploit extra or dummy wordlines in the memory device, wherein the extra wordlines are not part of a main memory area of the memory device but, when activated, connect their attached memory cells to the bitlines of the main memory area. The extra wordlines are connected to a voltage in such a manner so as to simulate a floating wordline condition. Associated with each extra wordline is a driver circuit that connects the extra wordline to a voltage to allow it to charge up to the voltage, and subsequently disconnects the wordline from the voltage to allow it to float. While the extra wordline is floating, measurements may be made on the memory device to gather data useful for testing production memory chips for floating wordline conditions. According to another aspect, one or more extra wordlines may be activated to connect its attached memory cells to bitlines, thereby increasing the capacitance on the bitlines. This is useful during certain test mode conditions of a memory device, or on a more permanent basis to enhance the performance of the memory device.