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    Method and apparatus for selectively connecting and setting each chip of semiconductor wafer
    1.
    发明专利
    Method and apparatus for selectively connecting and setting each chip of semiconductor wafer 审中-公开
    用于选择性地连接和设置半导体波片的每个芯片的方法和装置

    公开(公告)号：JP2007096268A

    公开(公告)日：2007-04-12

    申请号：JP2006187619

    申请日：2006-07-07

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： FUHRMANN DIRK ,  PERRY ROBERT ,  REHM NORBERT ,  UNG RATH ,  ZIELEMAN JAN

    IPC: H01L21/66

    CPC classification number: G01R31/31722 ,  G11C29/006 ,  G11C29/028 ,  G11C2029/0407 ,  G11C2029/2602 ,  G11C2029/4402 ,  G11C2029/5602

    Abstract: PROBLEM TO BE SOLVED: To provide a method and system which can obtain a method and apparatus setting wafer chips with a single power on and off sequence, and further adjust a chip parameter during a wafer test without utilizing the sequence.
    SOLUTION: The method comprises the steps of: assigning a specific identifier to a controllable chip resistor by a program of each wafer chip for test (step 52); storing a value of the parameter fixed by corresponding to each of them inside the chip resistor of the chip selected based on its identifier (step 54); and performing a test evaluating a setting of the parameter for each chip with a desired parameter set simultaneously (step 56).
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种方法和系统，其可以获得具有单个功率开启和关闭序列来设置晶片芯片的方法和装置，并且在晶片测试期间进一步调整芯片参数而不利用该序列。 该方法包括以下步骤：通过用于测试的每个晶片芯片的程序将特定标识符分配给可控芯片电阻器（步骤52）; 根据其标识符将所选择的芯片的片式电阻器中的每一个固定的参数的值存储在其中（步骤54）; 并且执行用同时设定的期望参数来评估每个芯片的参数的设置的测试（步骤56）。 版权所有（C）2007，JPO＆INPIT

    HYBRID FUSES FOR REDUNDANCY
    2.
    发明申请
    HYBRID FUSES FOR REDUNDANCY 审中-公开
    用于冗余的混合熔断器

    公开(公告)号：WO2004029971A3

    公开(公告)日：2004-06-03

    申请号：PCT/EP0310468

    申请日：2003-09-19

    Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KK

    Inventor： JOACHIM HANS-OLIVER ,  MIYAKAWA TADASHI ,  REHM NORBERT ,  ROEHR THOMAS

    IPC: G11C29/00

    CPC classification number: G11C29/785 ,  G11C17/14

    Abstract: A redundancy unit (204) comprising first (260) and second (270) fuse blocks for programming the redundancy element (220) is disclosed. One fuse block has laser blowable fuses and the other electrical fuses. The redundancy unit can be programmed by either one of the fuse blocks, enabling the redundancy unit to able to be used for defects identified before and after packaging.

    Abstract translation: 公开了一种包括用于对冗余元件（220）进行编程的第一（260）和第二（270））熔丝块的冗余单元（204）。 一个保险丝盒有激光熔断保险丝和其他电气保险丝。 冗余单元可以通过任一个保险丝块进行编程，使得冗余单元能够用于包装之前和之后识别的缺陷。

    REDUCING EFFECTS OF NOISE COUPLING IN INTEGRATED CIRCUITS WITH MEMORY ARRAYS
    3.
    发明申请
    REDUCING EFFECTS OF NOISE COUPLING IN INTEGRATED CIRCUITS WITH MEMORY ARRAYS 审中-公开
    噪声耦合在集成电路与存储器阵列中的降低效应

    公开(公告)号：WO2004051666A3

    公开(公告)日：2005-02-24

    申请号：PCT/EP0312715

    申请日：2003-11-13

    Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KK ,  JACOB MICHAEL ,  REHM NORBERT ,  ROEHR THOMAS ,  TAKASHIMA DAISABURO

    Inventor： JACOB MICHAEL ,  REHM NORBERT ,  ROEHR THOMAS ,  TAKASHIMA DAISABURO

    IPC: G11C11/22

    CPC classification number: G11C11/22

    Abstract: A method for reducing noise coupling in a memory array is disclosed. The memory array includes a plurality memory cells interconnected by wordlines, bitlines, and platelines. The memory cells are arranged in columns having first and second bitlines coupled to a sense amplifier. During a memory access, at least adjacent bitlines pairs are not activated. The selected bitline pair or pairs are provided with a plateline pulse.

    Abstract translation: 公开了一种减少存储器阵列中的噪声耦合的方法。 存储器阵列包括通过字线，位线和平行线互连的多个存储器单元。 存储器单元被布置成具有耦合到读出放大器的第一和第二位线的列。 在存储器访问期间，至少相邻的位线对不被激活。 选定的位线对或对配有一条平行线脉冲。

    IMPROVED MEMORY ARCHITECTURE
    4.
    发明申请
    IMPROVED MEMORY ARCHITECTURE 审中-公开
    改进的内存架构

    公开(公告)号：WO2004027779A2

    公开(公告)日：2004-04-01

    申请号：PCT/EP0309399

    申请日：2003-08-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： JACOB MICHAEL ,  REHM NORBERT ,  ROEHR THOMAS ,  WOHLFAHRT JOERG

    IPC: G11C11/22

    CPC classification number: G11C11/22

    Abstract: An IC with memory cells arranged in groups is described. The memory cells, for example, are ferroelectric memory cells. The IC includes a variable voltage generator (VVG) for generating an output voltage having a different voltage level depending on a location of an addressed memory cell within the memory group is provided. By providing different voltage levels for reads and/or writes, signal loss caused by capacitances which is dependent on the location of the memory cell within the group can be avoided. This improves read and/or write operations in series memory architectures.

    Abstract translation: 描述了具有按组排列的存储器单元的IC。 存储单元例如是铁电存储单元。 IC包括可变电压发生器（VVG），用于根据存储器组内被寻址的存储单元的位置产生具有不同电压电平的输出电压。 通过为读取和/或写入提供不同的电压电平，可以避免由取决于组内存储器单元的位置的电容引起的信号损失。 这改进了串行存储器体系结构中的读取和/或写入操作。

    5.
    发明专利
    未知

    公开(公告)号：DE102006030360A1

    公开(公告)日：2007-03-15

    申请号：DE102006030360

    申请日：2006-06-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FUHRMANN DIRK ,  PERRY ROBERT ,  REHM NORBERT ,  UNG RATH ,  ZIELEMAN JAN

    IPC: H01L21/66 ,  G01R31/28 ,  G11C29/48

    Abstract: A method and apparatus according to the present invention enable wafer chips to be configured with a single power on and off sequence and further enable a chip parameter to be adjusted during a wafer test without utilizing that sequence. In particular, each wafer chip under test is assigned a unique programmable identification. Once each chip has been assigned a corresponding identification, the chips may each be individually accessible by that identification to provide parameter values to chip registers to configure that chip. The configured chips may be subsequently tested in parallel to evaluate the parameter settings. In addition, the present invention enables chips to share data I/O pins or lines, thereby reducing the quantity of testing machine pins utilized for each chip and enabling a greater quantity of chips to be tested in a parallel fashion.

    7.
    发明专利
    未知

    公开(公告)号：DE102005050394A1

    公开(公告)日：2006-05-04

    申请号：DE102005050394

    申请日：2005-10-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： PERRY ROBERT ,  REHM NORBERT ,  ZIELEMAN JAN

    IPC: G11C29/12

    Abstract: A memory device and methods to exploit extra or dummy wordlines in the memory device, wherein the extra wordlines are not part of a main memory area of the memory device but, when activated, connect their attached memory cells to the bitlines of the main memory area. The extra wordlines are connected to a voltage in such a manner so as to simulate a floating wordline condition. Associated with each extra wordline is a driver circuit that connects the extra wordline to a voltage to allow it to charge up to the voltage, and subsequently disconnects the wordline from the voltage to allow it to float. While the extra wordline is floating, measurements may be made on the memory device to gather data useful for testing production memory chips for floating wordline conditions. According to another aspect, one or more extra wordlines may be activated to connect its attached memory cells to bitlines, thereby increasing the capacitance on the bitlines. This is useful during certain test mode conditions of a memory device, or on a more permanent basis to enhance the performance of the memory device.

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