公开(公告)号：JP2003197785A

公开(公告)日：2003-07-11

申请号：JP2002342967

申请日：2002-11-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SPECHT MICHAEL ,  STADELE MARTIN ,  ROSNER WOLFGANG ,  HOFFMANN FRANZ

IPC: H01L21/8247 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a floating gate field effect transistor as a nonvolatile data storage device wherein writing/erasing times practically are reduced as compared with a conventional technique in the state that at least the period of a holding time is not changed. SOLUTION: The floating gate field effect transistor (400) which is used as a memory cell is provided with a sequence (408) of an electrical insulating layer which contains a lower layer (409) having first relative permittivity, an intermediate layer (410) having second relative permittivity, and an upper layer (411) having third relative permittivity above or below a floating gate region (407). In this case, the second relative permittivity is greater than the first relative permittivity and greater than the third relative permittivity. COPYRIGHT: (C)2003,JPO

公开(公告)号：AU2003258649A1

公开(公告)日：2004-03-29

申请号：AU2003258649

申请日：2003-08-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFMANN FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROSNER WOLFGANG ,  SPECHT MICHAEL

IPC: G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01R11/22 ,  H01R13/62

Abstract: Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence in the longitudinal direction of the rib. The rib has an essentially rectangular shape with an upper side of the rib and rib side faces lying opposite. A memory layer is configured for programming the memory cell, arranged on the upper side of the rib spaced apart by a first insulator layer, and projects in the normal direction of the one rib side face over one of the rib side faces so that the one rib side face and the upper side of the rib form an edge for injecting charge carriers from the channel region into the memory layer. A gate electrode is spaced apart from the one rib side face by a second insulator layer and from the memory layer by a third insulator layer, electrically insulated from the channel region, and configured to control its electrical conductivity.

公开(公告)号：AU2003258649A8

公开(公告)日：2004-03-29

申请号：AU2003258649

申请日：2003-08-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LANDGRAF ERHARD ,  SPECHT MICHAEL ,  LUYKEN RICHARD JOHANNES ,  HOFMANN FRANZ ,  ROSNER WOLFGANG

IPC: G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01R11/22 ,  H01R13/62

Abstract: Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence in the longitudinal direction of the rib. The rib has an essentially rectangular shape with an upper side of the rib and rib side faces lying opposite. A memory layer is configured for programming the memory cell, arranged on the upper side of the rib spaced apart by a first insulator layer, and projects in the normal direction of the one rib side face over one of the rib side faces so that the one rib side face and the upper side of the rib form an edge for injecting charge carriers from the channel region into the memory layer. A gate electrode is spaced apart from the one rib side face by a second insulator layer and from the memory layer by a third insulator layer, electrically insulated from the channel region, and configured to control its electrical conductivity.