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    Layer arrangement and manufacturing method of layer arrangement
    1.
    发明专利
    Layer arrangement and manufacturing method of layer arrangement 审中-公开
    层布置的层布置和制造方法

    公开(公告)号：JP2006024940A

    公开(公告)日：2006-01-26

    申请号：JP2005198169

    申请日：2005-07-06

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： ILICALI GUERKAN ,  LANDGRAF ERHARD ,  ROESNER WOLFGANG ,  HOFFMANN FRANZ

    IPC: H01L29/786 ,  H01L21/02 ,  H01L21/336 ,  H01L27/12

    CPC classification number: H01L29/66772 ,  H01L29/66628 ,  H01L29/78648 ,  H01L29/78654

    Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a layer arrangement capable of overcoming a problem related to epitaxial growth.
    SOLUTION: In a manufacturing method of a layer arrangement of the present invention, a first layer (203) having a thickness larger than a minimum thickness for the epitaxial growth of a second layer (408) is formed, a second layer (408) is epitaxially grown on the first layer (203), and a third layer (409) is formed on the second layer (408). Further, a handling wafer (510) is joined on the third layer, and the substrate is removed from a second surface facing a first surface, and the first layer (203) is partially made to be thin from the second surface, and as a result, after making the layer thin, the first layer (203) has a thickness smaller than the minimum thickness for the epitaxial growth.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供能够克服与外延生长相关的问题的层布置的制造方法。 解决方案：在本发明的层布置的制造方法中，形成厚度大于第二层（408）的外延生长的最小厚度的第一层（203），第二层（ 408）在第一层（203）上外延生长，第三层（409）形成在第二层（408）上。 此外，处理晶片（510）接合在第三层上，并且从与第一表面相对的第二表面移除基板，并且第一层（203）部分地从第二表面变薄，并且作为 结果，在使薄层变薄之后，第一层（203）的厚度小于用于外延生长的最小厚度。 版权所有（C）2006，JPO＆NCIPI

    METHOD FOR PRODUCING A MEMORY CELL
    3.
    发明申请
    METHOD FOR PRODUCING A MEMORY CELL 审中-公开
    METHOD FOR CELL

    公开(公告)号：WO03067639A3

    公开(公告)日：2003-10-16

    申请号：PCT/DE0300183

    申请日：2003-01-23

    Applicant: INFINEON TECHNOLOGIES AG ,  HOFMANN FRANZ ,  LANDGRAF ERHARD ,  LUYKEN HANNES

    Inventor： HOFMANN FRANZ ,  LANDGRAF ERHARD ,  LUYKEN HANNES

    IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

    Abstract: The invention relates to NROM memory cells that are disposed in trenches that are etched into the semiconductor material. The memory layer composed of a nitride layer (3) that is interposed between two oxide layers (2, 4) is applied to the trench walls before the dopants for source and drain (7) are implanted. The implantation regions of source and drain are thus prevented from being damaged by the high temperature loads of the component during production of the memory layer as the respective dopant is introduced only later on. Polysilicon gate electrodes (5) are connected to word lines (11).

    Abstract translation: 的NROM存储单元被布置在被蚀刻到半导体材料中的沟槽。 氧化物层之间的氮化物层（3）的存储层（2,4）的掺杂剂为源极和漏极（7）到被植入之前施加到坟墓壁。 以这种方式，实现了在所述存储层的制造部件的高温负荷不能与源和漏区的注入干扰，如在讨论的掺杂剂将只随后引入。 由多晶硅制成的栅电极（5）被连接到字线（11）。

    HIGH-DENSITY NROM-FINFET
    6.
    发明申请
    HIGH-DENSITY NROM-FINFET 审中-公开
    HIGH POET NROM的FinFET

    公开(公告)号：WO2004023519A2

    公开(公告)日：2004-03-18

    申请号：PCT/EP0309297

    申请日：2003-08-21

    Applicant: INFINEON TECHNOLOGIES AG ,  HOFMANN FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SPECHT MICHAEL

    Inventor： HOFMANN FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SPECHT MICHAEL

    IPC: G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01R11/22 ,  H01R13/62 ,  H01L

    CPC classification number: H01L21/28273 ,  G11C16/0466 ,  H01L21/28282 ,  H01L21/845 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S257/905

    Abstract: The invention relates to a semiconductor memory comprising a plurality of memory cells, each memory cell comprising the following: a first conductively doped contact area (S/D), a second conductively doped contact area (S/D) and a channel region arranged therebetween, which are embodied in a plate-type rib (FIN) made of a semiconductor material and which are arranged successively in the above-mentioned order in the longitudinal direction of the rib (FIN), said rib (FIN) having a substantially rectangular shape, according to a cross-sectional view extending in a perpendicular manner with respect to the longitudinal direction of the rib (FIN), comprising an upper rib side (10) and opposite lateral rib surfaces (12, 14); a memory layer (18) which is embodied in order to program the memory cell and which is arranged on the upper rib side (10) and distanced by means a first insulating layer (20), said memory layer (18) protruding over at least one (12) of the lateral rib surfaces (12) in a normal direction of one lateral rib surface (12), such that said one lateral rib surface (12) and the upper rib surface (10) form an injection edge (16) for injecting charge carriers from the channel region into the memory layer (18); and at least one gate electrode (WL1) which is distanced by means of a second insulating layer (22) from said one lateral rib surface (12) and distanced by means of a third insulating layer (29) from the memory layer (18), said gate electrode (WL1) being electrically insulated in relation to the channel region and being embodied in order to control the electrical conductivity thereof.

    Abstract translation: 本发明涉及一种具有多个存储器单元，每个存储器单元包括一个半导体存储器：第一导电掺杂接触区（S / D），第二导电掺杂接触区（S / D）和一个介于沟道区，其中（在网状肋FIN ）形成的半导体材料，以及（在肋FIN的纵向方向上按此次序）被布置成一个在另一个后面，其中所述鳍（FIN）至少在垂直（在沟道区延伸到所述肋FIN的长度方向）截面，具有一肋顶部的大致rechtsecksförmige形状 （10）和相对的肋的侧表面（12，14）; 所设计的用于通过第一绝缘体层编程所述存储器单元存储层（18）（20）间隔开的肋顶部（10）布置，其中，在一个正常的方向经由肋的侧表面中的至少一个（12）（12）的存储层（18） 肋侧表面（12）突出，以使所述一个肋侧表面（12）和肋顶部（10）形成用于从沟道区的载流子到所述存储层注入（18）的喷射边缘（16）; 和至少一个栅极电极（WL1），其通过第二绝缘体层隔开一个（22）的肋侧表面（12）和通过所述存储层（18）的第三绝缘层（29），其中所述沟道区相对的栅电极（WL1），其电 是绝缘的，并适于控制其导电性。

    Laterales Transisterbauelement und Verfahren zu dessen Herstellung
    7.
    发明专利
    Laterales Transisterbauelement und Verfahren zu dessen Herstellung 未知

    公开(公告)号：DE102011122906A1

    公开(公告)日：2013-06-27

    申请号：DE102011122906

    申请日：2011-12-06

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： PRIBIL ANDREAS ,  DAHL CLAUS ,  FEICK HENNING ,  BERTRAMS THOMAS ,  LANDGRAF ERHARD

    IPC: H01L29/78 ,  H01L21/283 ,  H01L21/336 ,  H01L21/76 ,  H01L29/06

    Abstract: Beschrieben werden eine Transistorbauelement und ein Verfahren zur Herstellung einer Dielektrikumsschicht. Ein Ausführungsbeispiel des Transistorbauelements umfasst: einen Halbleiterkörper (100); ein in dem Halbleiterkörper (100) angeordnetes aktives Transistorgebiet (110); ein das aktive Transistorgebiet in dem Halbleiterkörper (100) ringförmig umgebendes Isolationsgebiet (120); eine Sourcezone (11), eine Drainzone (12), eine Bodyzone (13) und eine Driftzone (14) in dem aktiven Transistorgebiet (110), wobei die Sourcezone (11) und die Drainzone (12) in lateraler Richtung des Halbleiterkörpers (100) beabstandet sind und die Bodyzone (13) zwischen der Sourcezone (11) und der Driftzone (14) und die Driftzone (14) zwischen der Bodyzone (13) und der Drainzone angeordnet ist; eine Gate- und Feldelektrode (20), wobei die Gate- und Feldelektrode (20) oberhalb des aktiven Transistorgebiets (110) angeordnet ist und gegenüber dem aktiven Transistorgebiet (100) durch eine Dielektrikumsschicht (30) isoliert ist, die im Bereich der Bodyzone (13) eine erste Dicke (d1) und im Bereich der Driftzone (14) abschnittsweise eine zweite Dicke (d2), die größer als die erste Dicke (d1) ist, aufweist und wobei die Dielektrikumsschicht (30) einen Übergangsbereich (33) aufweist, in dem die Dicke von der ersten Dicke (d1) zu der zweiten Dicke (d2) zunimmt und in dem die Dielektrikumsschicht (30) wenigstens abschnittsweise unter einem Winkel kleiner als 90° gegenüber einer Seite (101) des Halbleiterkörper geneigt ist.

    High-density nrom-finfet
    9.
    发明专利
    High-density nrom-finfet 未知

    公开(公告)号：AU2003258649A8

    公开(公告)日：2004-03-29

    申请号：AU2003258649

    申请日：2003-08-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LANDGRAF ERHARD ,  SPECHT MICHAEL ,  LUYKEN RICHARD JOHANNES ,  HOFMANN FRANZ ,  ROSNER WOLFGANG

    IPC: G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01R11/22 ,  H01R13/62

    Abstract: Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence in the longitudinal direction of the rib. The rib has an essentially rectangular shape with an upper side of the rib and rib side faces lying opposite. A memory layer is configured for programming the memory cell, arranged on the upper side of the rib spaced apart by a first insulator layer, and projects in the normal direction of the one rib side face over one of the rib side faces so that the one rib side face and the upper side of the rib form an edge for injecting charge carriers from the channel region into the memory layer. A gate electrode is spaced apart from the one rib side face by a second insulator layer and from the memory layer by a third insulator layer, electrically insulated from the channel region, and configured to control its electrical conductivity.

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