公开(公告)号：DE102005024955B4

公开(公告)日：2007-06-21

申请号：DE102005024955

申请日：2005-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUEHLBACHER BENNO ,  GRATZ ACHIM ,  ROEHRICH MAYK ,  KRICKL EVELYN MARIA ,  WIESBAUER ANDREAS ,  SANSEGUNDOBELLO DAVID ,  POETSCHER THOMAS

IPC: H03K19/0185 ,  H03K19/003

公开(公告)号：DE102005024955A1

公开(公告)日：2006-12-07

申请号：DE102005024955

申请日：2005-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUEHLBACHER BENNO ,  GRATZ ACHIM ,  ROEHRICH MAYK ,  KRICKL EVELYN MARIA ,  WIESBAUER ANDREAS ,  SANSEGUNDOBELLO DAVID ,  POETSCHER THOMAS

IPC: H03K19/0185 ,  H03K19/003

Abstract: The circuit has a signal input (2) to apply logic signals having a signal-reference potential and a preset signal hub. A cascade protective circuit (14) is provided between low voltage transistor pairs (11, 13) to limit voltage drops in low voltage field effect transistors (11a, 11b, 13a, 13b) of both the pairs. A signal output is tapped in a gate connector of the transistors (13a, 13b) of the complementary pair (13) to output level shifted logic signals with a signal hub.