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    Semiconductor device and method of operating semiconductor device
    1.
    发明专利
    Semiconductor device and method of operating semiconductor device 审中-公开
    半导体器件和操作半导体器件的方法

    公开(公告)号：JP2006236560A

    公开(公告)日：2006-09-07

    申请号：JP2006049638

    申请日：2006-02-27

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： GRATZ ACHIM ,  ROEHRICH MAYK

    IPC: G11C16/04

    CPC classification number: G11C16/045 ,  G11C16/0441

    Abstract: PROBLEM TO BE SOLVED: To provide a nonvolatile memory being optimum for application requiring small quantity memory. SOLUTION: In a nonvolatile semiconductor memory device having first and second floating gate transistors coupled in series, the floating gate transistor has a floating gate. A programming means coupled to the first and second floating gate transistors are operable to place a selected electrical charge in one of the floating gates and less than the selected electrical charge in the other floating gate to represent either of a first or second binary value. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种非常适合需要少量存储器的应用的非易失性存储器。 解决方案：在具有串联耦合的第一和第二浮栅晶体管的非易失性半导体存储器件中，浮栅晶体管具有浮栅。 耦合到第一和第二浮栅晶体管的编程装置可操作以将选定的电荷放置在浮置栅极中的一个中，并且小于另一个浮置栅极中选定的电荷以表示第一或第二二进制值。 版权所有（C）2006，JPO＆NCIPI

    VERTICAL NON-VOLATILE SEMICONDUCTOR MEMORY CELL AND ITS MANUFACTURING METHOD
    2.
    发明专利
    VERTICAL NON-VOLATILE SEMICONDUCTOR MEMORY CELL AND ITS MANUFACTURING METHOD 审中-公开

    公开(公告)号：JP2002076153A

    公开(公告)日：2002-03-15

    申请号：JP2001255055

    申请日：2001-08-24

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GRATZ ACHIM

    IPC: H01L21/8242 ,  H01L21/8247 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/788 ,  H01L29/792

    Abstract: PROBLEM TO BE SOLVED: To improve data retention characteristics and retention time in a vertical non-volatile semiconductor memory cell. SOLUTION: A trench 5 is formed vertically to the surface of a board 20 from a source area 3 to a drain area 1 in the vertical direction. A first dielectric layer 8 formed on the wall of the trench, a charge accumulation layer 9 formed on the first dielectric layer 8, a second dielectric layer 10 formed on the surface of the charge accumulation layer 9, and control layers 11, 11' formed on the surface of the second dielectric layer 10 are provided. A trench extension part 5' is formed downward of the trench 5, and has a third dielectric layer 6 formed on the surface of the trench and a filling material 7 for at least partially filling the trench extension part 5'.

    SEMICONDUCTOR STRUCTURE AND METHOD FOR THE PRODUCTION THEREOF
    3.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD FOR THE PRODUCTION THEREOF 审中-公开
    半导体结构及其制造方法

    公开(公告)号：WO03038893A2

    公开(公告)日：2003-05-08

    申请号：PCT/EP0211853

    申请日：2002-10-23

    Applicant: INFINEON TECHNOLOGIES AG ,  GRATZ ACHIM ,  KRIZ JAKOB

    Inventor： GRATZ ACHIM ,  KRIZ JAKOB

    IPC: H01L21/8249 ,  H01L27/06

    CPC classification number: H01L27/0623 ,  H01L21/8249

    Abstract: The invention relates to a semiconductor structure and to a method for the production thereof, wherein a substrate (210) is provided with a first main surface and a recess (220) is made in the main surface of the substrate (210). An active area (244, 24, 250) of the conductor structure is created in the region of the bottom of the recess (220) and contact areas (252) of at least one part of the connections are made in the direction of the first surface of the substrate (210).

    Abstract translation: 本发明提供一种半导体结构及其制造方法，其中在具有第一主表面的衬底（210）上的衬底（210）的第一主表面中形成凹槽（220）。 此外，半导体结构的有源区域（244,246,250）在凹槽（220）底部的区域中产生，并且端子的至少一部分的引出区域（252）沿基板（210）的第一表面的方向引出。

    MEMORY CELL, MEMORY CELL DEVICE AND METHOD FOR THE PRODUCTION THEREOF
    4.
    发明申请
    MEMORY CELL, MEMORY CELL DEVICE AND METHOD FOR THE PRODUCTION THEREOF 审中-公开
    存储器单元，存储器单元布置和制造方法

    公开(公告)号：WO0215276A3

    公开(公告)日：2002-06-06

    申请号：PCT/DE0102997

    申请日：2001-08-06

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： PALM HERBERT ,  WILLER JOSEF ,  GRATZ ACHIM ,  KRIZ JAKOB ,  ROEHRICH MAYK

    IPC: H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

    Abstract: Each memory cell is a memory transistor which is provided with a gate electrode (2) on the upper surface of a semiconductor body. Said gate electrode is disposed in a trench between a source area (3) and a drain area (4) which are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by dielectric material. A series of oxide nitride-oxide layers (5, 6, 7) is disposed between the source area and the drain area and between the drain area and the gate electrode in order to capture charge carriers on the source and drain.

    Abstract translation: 每个存储器单元是设置在半导体主体的顶表面上的存储器晶体管，其中栅极电极（2）设置在形成在半导体材料中的源极区（3）和漏极区（4）之间的沟槽中 形成。 栅电极通过介电材料与半导体材料分离。 至少在源区和栅电极之间以及在漏区和栅电极之间存在氧化物 - 氮化物 - 氧化物层序列（5,6,7），其适于在源极和漏极处捕获电荷载流子 被提供。

    METHOD FOR PRODUCING BIT LINES FOR UCP FLASH MEMORIES
    5.
    发明申请
    METHOD FOR PRODUCING BIT LINES FOR UCP FLASH MEMORIES 审中-公开
    制造用于UCP闪存的位的方法

    公开(公告)号：WO2004068578A3

    公开(公告)日：2004-10-28

    申请号：PCT/DE2004000042

    申请日：2004-01-15

    Applicant: INFINEON TECHNOLOGIES AG ,  GRATZ ACHIM ,  POLEI VERONIKA ,  ROEHRICH MAYK

    Inventor： GRATZ ACHIM ,  POLEI VERONIKA

    IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

    CPC classification number: H01L27/11521 ,  H01L27/115

    Abstract: The invention relates to a method for producing bit lines for UCP flash memories comprising a floating gate arrangement arranged on a substrate and an insulation arranged in the substrate under the floating gate arrangement. Initially, the floating gate is produced, after photolithography, by etching a separated polysilicon layer deposited on the total surface of the substrate. The aim of the invention is to provide a method wherein cell size can be reduced without significantly increasing production costs and wherein the bit lines survive the temperature budget of the sequence process without being damaged. As a result, the bit line (13), embodied as a buried bit line made of a temperature resistant material, is arranged in a silicon substrate (2) or in the insulation (3) of the active area below the floating gate (1) by automatic adjustment therewith (2). The already structured floating gate (1) is used as an etching mask for producing, by etching in insulation (3), a trench (6) which is subsequently filled with a low impedance material.

    Abstract translation: 本发明涉及一种用于为UCP快闪存储器位线的制造具有设置在基板上浮动栅极组件和所述浮置栅极器件下的衬底中的隔离方法，其特征在于，最初的浮置栅极通过现有的光刻通过在基板上蚀刻 产生位于整个区域上方的沉积多晶硅层。 本发明的目的是提供一种方法，通过该方法可以实现单元尺寸的减小，生产成本受到的影响可以忽略不计，并且位线在后续工艺的温度预算下不会受到损坏。 实现，即，位线（13）在硅衬底（2）由耐温度变化的材料掩埋位线或绝缘（3）内的浮置栅（1）是，自对准于该布置下的有源区。 在这种情况下，使用已经构造的浮置栅极（1）作为蚀刻掩模将沟槽（6）蚀刻到绝缘体（3）中，然后用低电阻材料填充该蚀刻掩模。

    VORRICHTUNGSKONTAKTFLECKE ÜBER PROZESSSTEUERUNGS-/ÜBERWACHUNGS-STRUKTUREN IN EINEM HALBLEITERCHIP
    7.
    发明专利
    VORRICHTUNGSKONTAKTFLECKE ÜBER PROZESSSTEUERUNGS-/ÜBERWACHUNGS-STRUKTUREN IN EINEM HALBLEITERCHIP 未知

    公开(公告)号：DE102014102087A1

    公开(公告)日：2014-08-21

    申请号：DE102014102087

    申请日：2014-02-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GRATZ ACHIM ,  JACOBS TOBIAS ,  WALLACE SCOTT

    IPC: H01L23/522 ,  H01L21/60 ,  H01L21/768 ,  H01L23/544

    Abstract: Ein Halbleiterchip enthält ein Halbleitersubstrat mit einem einen aktiven Bereich (104) umgebenden Randbereich (106), wobei der aktive Bereich (104) Vorrichtungen einer integrierten Schaltung enthält. Der Halbleiterchip enthält ferner Leiterbahnverdrahtung (108) über dem aktiven Bereich (104) in einem Zwischenschichtdielektrikum (110), wobei die Leiterbahnverdrahtung (108) elektrisch mit den Vorrichtungen im aktiven Bereich (104) verbunden ist, und Zusatzverdrahtung (118) über dem Randbereich (106) im Zwischenschichtdielektrikum (110), wobei die Zusatzverdrahtung (118) von der Leiterbahnverdrahtung (108) und den Vorrichtungen im aktiven Vorrichtungsbereich isoliert ist. Das Zwischenschichtdielektrikum (110) ist passiviert und Kontaktpads (124) sind über der Leiterbahnverdrahtung (108) bereitgestellt, wobei die Kontaktpads (124) durch Öffnungen in der Passivierung (122) über dem aktiven Bereich (104) elektrisch mit der Leiterbahnverdrahtung (108) verbunden sind. Zusätzliche Kontaktpads (126) sind über der Zusatzverdrahtung (118) bereitgestellt, wobei die zusätzlichen Kontaktpads (126) durch zusätzliche Öffnungen in der Passivierung (122) über dem aktiven Bereich (104) elektrisch mit der Zusatzverdrahtung (118) verbunden sind.

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