公开(公告)号：JP2003023110A

公开(公告)日：2003-01-24

申请号：JP2002159754

申请日：2002-05-31

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： RICHTER FRANK ,  TEMMLER DIETMAR

IPC: G11C7/00 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10867 ,  H01L27/10832

Abstract: PROBLEM TO BE SOLVED: To provide memory cell structure having memory cells guaranteeing the simple connection of a small necessary area.
SOLUTION: The memory cells (15a, 15b and 15c) which are regularly arranged on a semiconductor piece are provided with trench capacitors (20a, 20b and 20c) formed on a semiconductor substrate (10), selection transistors (30a, 30b and 30c) formed on the capacitors and self-matching selection transistors (301, 30b and 30c)/memory trench contact parts (40a and 40b)/trench insulating part (52) structures.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供具有保证小的必要区域的简单连接的存储单元的存储单元结构。 解决方案：规则地布置在半导体片上的存储单元（15a，15b和15c）设置有形成在半导体衬底（10）上的沟槽电容器（20a，20b和20c），选择晶体管（30a，30b和30c） 形成在电容器和自匹配选择晶体管（301,30b和30c）/存储器沟槽接触部分（40a和40b）/沟槽绝缘部分（52）结构上。

公开(公告)号：JP2003037189A

公开(公告)日：2003-02-07

申请号：JP2002169778

申请日：2002-06-11

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： KUESTERS KARL HEINZ ,  TEMMLER DIETMAR

IPC: H01L21/8242 ,  H01L27/108 ,  H01L27/12

CPC classification number: H01L27/10867 ,  H01L27/10832 ,  H01L27/1203

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a dynamic memory cell as well as a semiconductor memory comprising the memory cell, related to a semiconductor substrate comprising a trench capacitor 1 and a switching transistor 2.
SOLUTION: Dielectric insulating layers 107 and 201 are formed between the switching transistor 2 and the trench capacitor 1. A contact opening 213 comprising a conductive contact-filling layer 214 is disposed almost above a polysilicon filling layer 102, which is an internal electrode of block type, of the trench capacitor 1, being positioned above the insulating layers 107 and 201. The contact opening 213 is coupled with a second diffusion region 204 of the switching transistor 2.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种制造动态存储单元的方法以及包括存储单元的半导体存储器，涉及包括沟槽电容器1和开关晶体管2的半导体衬底。解决方案：介电绝缘层107和201 形成在开关晶体管2和沟槽电容器1之间。包括导电接触填充层214的接触开口213几乎位于沟槽电容器1的作为块型内部电极的多晶硅填充层102的几乎上方， 位于绝缘层107和201的上方。接触开口213与开关晶体管2的第二扩散区204耦合。

公开(公告)号：WO0117019A3

公开(公告)日：2001-05-10

申请号：PCT/DE0002866

申请日：2000-08-23

Applicant: INFINEON TECHNOLOGIES AG ,  TEMMLER DIETMAR ,  BENZINGER HERBERT ,  KARCHER WOLFRAM ,  PUSCH CATHARINA ,  SCHREMS MARTIN ,  FAUL JUERGEN

Inventor： TEMMLER DIETMAR ,  BENZINGER HERBERT ,  KARCHER WOLFRAM ,  PUSCH CATHARINA ,  SCHREMS MARTIN ,  FAUL JUERGEN

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10861 ,  H01L27/10832

Abstract: The invention comprises a memory with a storage cell (100) that is formed in a substrate (105) and consists of a trench capacitor (110) and a transistor (160). The trench capacitor (110) is connected to the transistor (160) with a self-aligned connection (220). The transistor (160) at least partially covers said trench capacitor (110). The trench capacitor (110) is filled with a conductive trench filling and an insulating cover layer (135) is located on said conductive trench filling (130). An epitaxy layer (245) is located above said insulating cover layer (135). The transistor (160) is formed in said epitaxy layer (245). The self-aligned connection (220) is formed in a contact trench (205) and consists of an insulation collar (235) into which a conductive material (225) is introduced. A conductive cap (230) is formed on said conductive material.

Abstract translation: 本发明包括具有存储单元（100）的存储器，存储单元（100）形成在衬底（105）中并由沟槽电容器（110）和晶体管（160）组成。 沟槽电容器（110）通过自对准端子（220）连接到晶体管（160）。 晶体管（160）至少部分地覆盖沟槽电容器（110）。 沟槽电容器（110）填充有导电沟槽填充物（130），并且在导电沟槽填充物（130）上是绝缘覆盖层（135）。 绝缘覆盖层（135）之上是外延层（245）。 晶体管（160）形成在外延层（245）中。 自对准端子（220）形成在接触沟槽（205）中并且由其中引入导电材料（225）的绝缘轴环（235）组成。 在导电材料上形成导电帽（230）。

公开(公告)号：WO02073657A3

公开(公告)日：2003-05-22

申请号：PCT/DE0200788

申请日：2002-03-05

Applicant: INFINEON TECHNOLOGIES AG ,  GUSTIN WOLFGANG ,  GRUENING VON SCHWERIN ULRIKE ,  TEMMLER DIETMAR ,  SCHREMS MARTIN ,  RONGEN STEFAN ,  STRASSER RUDOLF

Inventor： GUSTIN WOLFGANG ,  GRUENING VON SCHWERIN ULRIKE ,  TEMMLER DIETMAR ,  SCHREMS MARTIN ,  RONGEN STEFAN ,  STRASSER RUDOLF

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10867 ,  H01L27/10873

Abstract: According to the invention, a trench capacitor is formed inside a trench (30) that is arranged inside a substrate (20). The trench (30) is filled with a conductive trench filling (50) that serves as an inner capacitor electrode. An epitaxial layer (75) is grown on the lateral wall of the trench (30) on the substrate (20). A buried contact (60) is arranged between the conductive trench filling (50) with the second intermediate layer (65) and the epitaxially grown layer (75). A dopant out-diffusion (80), which is formed while leading out from the buried contact (60), is arranged inside the epitaxially grown layer (75). The epitaxially grown layer (75) enables the dopant out-diffusion (80) to be further removed from a selection transistor (10) located next to the trench whereby permitting the prevention of short channel effects in the selection transistor (10).

Abstract translation: 它是在一个沟槽30，其被布置在基底20的严重电容器形成 沟槽30填充有导电填充严重50作为内部电容器电极。 在沟槽30的基板20上的侧壁，外延层75生长。 导电填充坟50与第二中间层65和外延生长层75，掩埋接触60布置之间。 在一个Dotierstoffausdiffusion 80被布置在外延生长层75，这是从所述掩埋接触60出来而形成。 通过外延生长层75，Dotierstoffausdiffusion 80进一步远离相邻排列的选择晶体管10，从而短沟道效应可以在选择晶体管10度可以避免沟槽。

公开(公告)号：WO02101824A3

公开(公告)日：2003-08-28

申请号：PCT/DE0202046

申请日：2002-06-05

Applicant: INFINEON TECHNOLOGIES AG ,  RICHTER FRANK ,  TEMMLER DIETMAR ,  WICH-GLASEN ANDREAS

Inventor： RICHTER FRANK ,  TEMMLER DIETMAR ,  WICH-GLASEN ANDREAS

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10867 ,  H01L27/10832 ,  H01L27/10873

Abstract: A memory cell (10) is embodied with a selection transistor (60) and a trench capacitor (30). The trench capacitor (30) is filled with a conducting trench filling (35), upon which an insulating cover layer (40) is arranged. A selectively grown epitaxial layer (45) is laterally grown over the insulating cover layer, starting from the substrate (15). The selection transistor (60) is embodied in the selectively grown epitaxial layer (45) and comprises a source region (65), for connection to the trench capacitor (30) and a drain region (70) for connection to a bitline. The junction depth of the source region (65) is selected such that the source region (65) extends as far as the insulating cover layer (40). In addition the thickness (50) of the epitaxial layer (45) may be optionally reduced to a suitable thickness by means of an oxidation and a subsequent etching. A contact trench (95) is then etched through the source region (65) as far as the conducting trench filling (35), which is filed with a conducting contact (90) and the conducting trench filling (35) electrically connected to the source region (65).

Abstract translation: 形成有具有选择晶体管（60）和一个电容器严重（30）的存储单元（10）。 坟墓电容器（30）被填充有导电填充严重（35），在其上的绝缘层（40）被布置。 覆盖绝缘层是横向地，从基板（15）配有一个选择性地生长外延层（45）生长开始。 在选择晶体管的选择性生长的外延层（45）（60）形成，并且在这种情况下包括连接到位线的源极区（65）以与严重电容器（30）连接，并且漏极区域（70） 要被连接的。 源极区（65）的结深度现在被选择为使得源极区（65）延伸直到所述绝缘覆盖层（40）。 任选地，通过氧化和随后的蚀刻的装置的外延层（45）的厚度（50）可以减少到适当的厚度。 接着，通过接触沟槽（95），以在导电严重填充所述源极区（65）（35）被蚀刻时，其被填充有导电接触（90）和所述导电严重填充（35）电性（与源极区域 65）连接。

公开(公告)号：WO03015159A3

公开(公告)日：2003-10-09

申请号：PCT/EP0208247

申请日：2002-07-24

Applicant: INFINEON TECHNOLOGIES AG ,  TEMMLER DIETMAR ,  WICH-GLASEN ANDREAS

Inventor： TEMMLER DIETMAR ,  WICH-GLASEN ANDREAS

IPC: H01L21/762

CPC classification number: H01L21/76229

Abstract: The invention relates to a trench isolation comprising a self-adjusting surface seal, and to a method for producing said surface seal. The surface seal can comprise an overlapping region of the substrate surface or a reconstituted region in which an electroconductive layer extends, said layer being formed on the substrate surface.

Abstract translation: 本发明涉及一种具有自密封表面和用于这些表面密封的制造方法的严重绝缘。 密封面可以具有在基板表面的重叠区域或者其中形成在所述基板表面的导电层上延伸的电极的背面形成区域。

公开(公告)号：WO02071474A3

公开(公告)日：2002-11-28

申请号：PCT/EP0201786

申请日：2002-02-20

Applicant: INFINEON TECHNOLOGIES AG ,  TEMMLER DIETMAR ,  WICH-GLASEN ANDREAS

Inventor： TEMMLER DIETMAR ,  WICH-GLASEN ANDREAS

IPC: H01L21/762

CPC classification number: H01L21/76235

Abstract: The invention relates to a method for broadening active semiconductor areas (2) on a semiconductor substrate (1) that has at least one trench isolation (3). The method is composed of the following steps: deposition of a pad-oxide layer (5) on a surface (4) of the semiconductor substrate (1); deposition of a pad-nitride layer (6) on the pad-oxide layer (5); structuring of the pad-nitride layer (6) to create at least one opening in the pad-nitride layer (6) and etching of the trench isolation(s) (3) in the pad-oxide layer (5) and the semiconductor substrate (1). The aim of the invention is to adjust the broadening of the structures of active semiconductor areas in a simple and cost-effective manner that is substantially independent of other process steps during the production of the component. To achieve this, the inventive method is characterised by the selective deposition of an epitaxy layer (7) with a predetermined thickness and by the oxidation of the surface (4) of the semiconductor substrate (1), to create a thin oxide layer (9) for passivation.

Abstract translation: 本发明涉及一种用于（2）在半导体衬底上加宽的有源半导体区域（1）具有至少一个严重绝缘（3），下裆个，在一个Oberflä枝沉积垫氧化物层（5）（4） 在半导体基板（1）; 衬垫氧化物层上沉积垫氮化物层（6）（5）; 在垫氮化物层（6），产生至少一个截止电压以及蚀刻所述至少一个严重绝缘（3）在焊盘氧化物层（5）和在所述半导体衬底进行构图的衬垫氮化物层（6）（1）。到 结构宽度的有源半导体区域，以独立于其它工艺步骤SET-LEN在器件的制造中以简单和成本有效的方式基本上，本发明的方法被标记在通过选择性地沉积具有预定厚度的外延层（7）和氧化表面（4 ），用于生成用于钝化的薄O型xidschicht（9）的半导体衬底（1）的。

公开(公告)号：DE10345460B4

公开(公告)日：2007-01-04

申请号：DE10345460

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUNDALKURKI SRIVATSA ,  TEMMLER DIETMAR ,  MOLL HANS-PETER ,  WIEDEMANN JOERG

IPC: H01L21/8242 ,  H01L21/20 ,  H01L29/76

Abstract: To fabricate a hole trench storage capacitor having an inner electrode, which is formed in a hole trench, and an outer electrode, which is formed in an electrode section, surrounding the hole trench in a lower section, of the semiconductor substrate, the inner electrode is continued above the substrate surface of the semiconductor substrate. Then, an additional layer, which widens the semiconductor substrate, is grown onto the substrate surface by an epitaxy process. A transition surface for contact-connection of the inner electrode and at least a part of an insulation collar is formed above the original substrate surface, thereby increasing the size of a surface area of the hole trench storage capacitor, which can be used for charge storage, while using the same aspect ratio for an etch used to form the hole trench.

公开(公告)号：DE10131237B8

公开(公告)日：2006-08-10

申请号：DE10131237

申请日：2001-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  RICHTER FRANK ,  POPP MARTIN ,  WICH-GLASEN ANDREAS

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06

Abstract: A transistor is provided which advantageously utilizes a part of the area which, in conventional transistors, is provided for the isolation between the transistors. In this case, the channel width can be enlarged in a self-aligned manner without the risk of short circuits. The field-effect transistor according to the invention has the advantage that it is possible to ensure a significant increase in the effective channel width for the forward current ION compared with previously used, conventional transistor structures, without having to accept a reduction of the integration density that can be attained. Thus, by way of example, the forward current I ON can be increased by up to 50%, without having to alter the arrangement of the active regions or of the trench isolation.

公开(公告)号：DE10202139B4

公开(公告)日：2006-07-13

申请号：DE10202139

申请日：2002-01-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POPP MARTIN ,  TEMMLER DIETMAR

IPC: H01L27/108 ,  H01L21/8242 ,  H01L23/48

Abstract: A memory cell in a substrate (105) comprises a select transistor (160) and connected trench capacitor (110) surrounded by an second isolation layer (150). A first adjacent isolation layer (235) is thinner than the second layer but prevents lateral current flow, although the formation of a parasitic FET through cell operation is possible. An Independent claim is also included for a memory chip as above.