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    Working memory testing circuit and method for personal computer containing Synchronous Dynamic Random Access Memory uses additional inserted card
    2.
    发明专利
    Working memory testing circuit and method for personal computer containing Synchronous Dynamic Random Access Memory uses additional inserted card 未知

    公开(公告)号：DE10007177A1

    公开(公告)日：2001-09-06

    申请号：DE10007177

    申请日：2000-02-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MOSER MANFRED ,  SCHRAMM ACHIM ,  DOLL ANDREAS

    IPC: G11C29/56 ,  G11C29/00

    Abstract: The system includes an ISA (Industry Standard Architecture) card (21) containing an SRAM (Static Random Access Memory) (22) and a Post Message Display Logic. The card, when it is installed, is connected via an ISA Bus (11) to the SDRAM (Synchronous Dynamic Random Access Memory). The system may use the following steps:- (1) Storage of at least one test command sequence in machine code in additional memory separate from working memory. (2) The machine code is activated in the PC and the CACHE store is activated. (3) The CPU is set in UNREAL-MODE so that data segmentation of the working store is cleared. (4) Previously arranged settings of the PC chips are run for the activation sequence for the test module. (5) A test module is chosen for implementing the activation sequence in the SDRAM. Data may be read from the additional store, so that. (6) The test module is activated by a given sequence of commands and addresses from the store or memory controller. (7) Test protocols are carried out.

    5.
    发明专利
    未知

    公开(公告)号：DE10135814C2

    公开(公告)日：2003-09-18

    申请号：DE10135814

    申请日：2001-07-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHNEIDER HELMUT ,  SCHRAMM ACHIM

    IPC: G11C7/12 ,  G11C8/08 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/407

    Abstract: The application of a nonactive level to a word line in a semiconductor memory is controlled by a precharge control. In order to initiate the precharge operation, a pair of reference bit lines are provided to which initially different potentials can be fed, which are subsequently amplified by a reference sense amplifier. The potential of one of the reference bit lines is amplified in a differential amplifier in order thereupon to cause a control device to initiate the precharge operation.

    6.
    发明专利
    未知

    公开(公告)号：DE10135814A1

    公开(公告)日：2003-02-13

    申请号：DE10135814

    申请日：2001-07-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHNEIDER HELMUT ,  SCHRAMM ACHIM

    IPC: G11C7/12 ,  G11C8/08 ,  G11C11/408 ,  G11C11/4094

    Abstract: The application of a nonactive level to a word line in a semiconductor memory is controlled by a precharge control. In order to initiate the precharge operation, a pair of reference bit lines are provided to which initially different potentials can be fed, which are subsequently amplified by a reference sense amplifier. The potential of one of the reference bit lines is amplified in a differential amplifier in order thereupon to cause a control device to initiate the precharge operation.

    Test method for output signals of integrated circuit e.g. for dynamic memory modules, integrated circuit has terminals for applying first- and second-data signals
    9.
    发明专利
    Test method for output signals of integrated circuit e.g. for dynamic memory modules, integrated circuit has terminals for applying first- and second-data signals 未知

    公开(公告)号：DE10340917A1

    公开(公告)日：2005-04-07

    申请号：DE10340917

    申请日：2003-09-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BEER PETER ,  SCHRAMM ACHIM ,  VERSEN MARTIN

    IPC: G11C29/50 ,  G11C29/00

    Abstract: A method for checking whether signals output through a write circuit of an integrated circuit results according to a given specification, in which a first data signal and associated second data signal can be outputted in a time relationship to one another, in which the specification defines a time offset value between the two data signals. The integrated circuit has a signal read circuit, in which at least two terminals are provided for applying the two data signals and in which each of the terminals is joined to the write circuit (6,8) and the read circuit (5). Initially, an external first calibration signal is prepared, then the read circuit is adjusted such that a threshold between a recognition and a non-recognition of the first calibration signal corresponds mainly to the time offset value. A first and second test data signal is prepared from the verifying write circuit and the prepared test data is then compared with the test data received from the read circuit (5), with an error detected when the two deviate. An independent claim is also included for a device for checking signals output.

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