公开(公告)号：JP2002334597A

公开(公告)日：2002-11-22

申请号：JP2002127431

申请日：2002-04-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUKAS RUPERT ,  PROELL MANFRED

IPC: G11C29/34 ,  G06F11/263 ,  G11C29/00 ,  G11C29/14

Abstract: PROBLEM TO BE SOLVED: To provide a method by which a write-in time for a cell array of a DRAM which comprises a semiconductor memory, especially, word lines and bit lines and in which a cell of a cell array is decided at an intersection point of these lines can be largely and surely shortened more than conventional one. SOLUTION: All bit lines BL in one word line WL are opened by logical combination of a column activation signal CAS and a test mode signal TM, a test data pattern is written simultaneously in all cells in the word line ML.

公开(公告)号：WO2004075197A3

公开(公告)日：2005-03-03

申请号：PCT/EP2004050207

申请日：2004-01-14

Applicant: INFINEON TECHNOLOGIES AG ,  STAVROU EVANGELOS ,  PROELL MANFRED ,  SCHROEDER STEPHAN ,  KLIEWER JOERG

Inventor： STAVROU EVANGELOS ,  PROELL MANFRED ,  SCHROEDER STEPHAN ,  KLIEWER JOERG

IPC: G11C11/15 ,  G11C11/16

CPC classification number: G11C11/15

Abstract: The invention relates to an MRAM memory cell in which the magnetic layers (ML1, ML2) separated by an intermediate layer (ZS) are made at least in part of a ferromagnetic material.

Abstract translation: 本发明涉及一种MRAM存储单元，其特征在于，通过一个中间层（ZS）分开磁性层（ML1，ML2）所述至少部分由铁磁材料构成。

公开(公告)号：DE102004022326B4

公开(公告)日：2008-04-03

申请号：DE102004022326

申请日：2004-05-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WIRKER BJOERN ,  PROELL MANFRED ,  KLIEWER JOERG ,  VAN DER ZANDEN KOEN

IPC: G11C29/02 ,  G11C7/12 ,  G11C8/00 ,  G11C11/4091 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56

Abstract: An integrated semiconductor memory can be operated in a normal operating state synchronously with a control clock. In the test operating state, the integrated semiconductor memory is driven synchronously with a clock edge of the control clock with a first control signal and starts a test run independent of the control clock. Driving with the first control signal, selection transistors in a memory bank that can be selected by a memory bank address are turned off. Afterward, bit lines in the selected memory bank are interconnected and driven with a predetermined precharge potential. After a precharge time has elapsed, one of the word lines is selected by an applied word line address and the selection transistors in the selected memory bank connected to the selected word line are turned on. Precharge times are set and tested independently of the clock period of the control clock.

公开(公告)号：DE102004022327B4

公开(公告)日：2006-04-27

申请号：DE102004022327

申请日：2004-05-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AUGE JUERGEN ,  PROELL MANFRED ,  SCHROEPPEL FRANK ,  KLIEWER JOERG

IPC: G11C29/00 ,  G11C7/00 ,  G11C29/48

Abstract: An integrated semiconductor memory includes a memory cell array with at least one memory cell, in which a data value is stored, and an evaluation circuit with a counter. During a test of the integrated semiconductor memory, a counter reading of the counter is altered if the data value stored in the memory cell deviates from a desired value. A threshold value is predefined by a control circuit. A programming circuit compares the threshold value on the input side with the instantaneous counter reading of the counter. If the counter reading of the counter exceeds the threshold value, a programming element changes from a first programming state to a second programming state. After the conclusion of the test, the state of the programming element is read out via an output terminal. This scheme makes it possible to deduce a possible cause of failure of the integrated semiconductor memory.

公开(公告)号：DE102004044150A1

公开(公告)日：2006-03-30

申请号：DE102004044150

申请日：2004-09-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEDER STEPHAN ,  PROELL MANFRED ,  AUGE JUERGEN ,  FISCHER HELMUT

IPC: G11C29/06

公开(公告)号：DE102004022425A1

公开(公告)日：2005-12-01

申请号：DE102004022425

申请日：2004-05-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PROELL MANFRED ,  KLIEWER JOERG ,  SCHNEIDER RALF ,  SCHROEDER STEPHAN

IPC: G05F1/595 ,  G11C5/14 ,  G11C7/00 ,  G11C11/4074

Abstract: An integrated circuit includes an input terminal (IN) for application of a supply voltage (Vext) and an output terminal (A) for generation of an output voltage (Vout). A first branch including a first controllable resistance (T 1 ) and a second branch including a charge pump ( 10 ) and a second controllable resistance (T 2 ) are connected between the input terminal (IN) and the output terminal (A). A control circuit ( 20 ) alters the resistance values of the first and second controllable resistances (T 1 , T 2 ) in a manner dependent on a ratio of an actual value (Vout) of the output voltage to a desired value (VSout) of the output voltage and a ratio of an actual value (Vext) of the supply voltage to a desired value (VSext) of the supply voltage. As a result, the output voltage (Vout) can be stabilized to the desired value (VSout) virtually independently of fluctuations of the supply voltage.

公开(公告)号：DE10358038A1

公开(公告)日：2005-07-21

申请号：DE10358038

申请日：2003-12-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER RALF ,  SCHROEDER STEPHAN ,  PROELL MANFRED ,  AUGE JUERGEN

IPC: G11C7/00 ,  G11C11/407 ,  G11C16/04 ,  G11C29/44

Abstract: An integrated circuit includes a programming circuit ( 10 ) for generating programming signals (PS 1 , . . . , PS 4 ) with a first input terminal (E 1 ) for applying a control voltage (ES), a second input terminal (E 2 ) for applying a reference voltage (Vref), a storage circuit ( 30 ) with programmable switches ( 35, . . . , 38 ) and output terminals (A 1 , . . . , A 4 ). The programming circuit in each case generates a programming signal (PS 1 , . . . , PS 4 ) when the control voltage (ES) exceeds a predefined threshold voltage formed from the reference voltage. The number of programming signals (PS 1 , . . . , PS 4 ) is dependent on the magnitude of the threshold voltage exceeded by the control voltage (ES). The programming signals are used for programming the programmable switches ( 35, . . . , 38 ). The programming state of the programmable switches can be read out via the output terminals (A 1 , . . . , A 4 ) of the integrated circuit. The integrated circuit enables the storage of external operating parameters of the integrated circuit.

公开(公告)号：DE10323501B4

公开(公告)日：2005-03-10

申请号：DE10323501

申请日：2003-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BENZINGER HERBERT ,  PROELL MANFRED ,  SCHROEDER STEPHAN ,  ZANDEN KOEN VAN DER

IPC: G11C5/14 ,  G11C7/04 ,  G11C7/06 ,  G11C7/12 ,  G11C11/34 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4091

Abstract: A circuit arrangement for setting a voltage supply for a read/write amplifier of an integrated memory has a first voltage generator circuit for generating a supply voltage for application to the read/write amplifier during an assessment and amplification operation and a second voltage generator circuit for generating a precharge voltage for precharging bit lines of the memory which are connected to the read/write amplifier. A temperature detector circuit, which is connected to the first voltage generator circuit, is used to detect a temperature of the memory and interacts with the first voltage generator circuit to set the supply voltage applied to the read/write amplifier in a manner depending on a temperature of the memory.

公开(公告)号：DE10311373B4

公开(公告)日：2005-02-24

申请号：DE10311373

申请日：2003-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEDER STEPHAN ,  KLIEWER JOERG ,  CAMPENHAUSEN AUREL VON ,  PROELL MANFRED

IPC: G11C7/00 ,  G11C29/00 ,  G11C29/44

Abstract: An integrated memory has individually addressable normal and redundant units of memory cells. A memory unit is used to store, in a normal mode, an address for one of the normal units which needs to be replaced by one of the redundant units. A comparison unit compares an address which is present on an address bus with an address stored in the memory unit and activates one of the redundant units in the event of a match being identified. The memory also has a test circuit which can be activated by a test mode signal, can reset the memory unit to an initial state, and can store an address for one of the redundant units in the memory unit for subsequently writing an identification code to this redundant unit.

公开(公告)号：DE10323501A1

公开(公告)日：2004-12-30

申请号：DE10323501

申请日：2003-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BENZINGER HERBERT ,  PROELL MANFRED ,  SCHROEDER STEPHAN ,  ZANDEN KOEN VAN DER

IPC: G11C5/14 ,  G11C7/04 ,  G11C7/06 ,  G11C7/12 ,  G11C11/34 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4091

Abstract: A circuit arrangement for setting a voltage supply for a read/write amplifier of an integrated memory has a first voltage generator circuit for generating a supply voltage for application to the read/write amplifier during an assessment and amplification operation and a second voltage generator circuit for generating a precharge voltage for precharging bit lines of the memory which are connected to the read/write amplifier. A temperature detector circuit, which is connected to the first voltage generator circuit, is used to detect a temperature of the memory and interacts with the first voltage generator circuit to set the supply voltage applied to the read/write amplifier in a manner depending on a temperature of the memory.